Custom IC Design

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RelXpert simulation error

Category: Custom IC Design

By rohit halba

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updated over 10 years ago by Andrew Beckett

1 replies • 14795 views
Discussion

Ultrasim: Cannot get the rectangular coordinates of resistors in Netlist-Based EM/IR Flow

Category: Custom IC Design

By Cuong Truong

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updated over 10 years ago by Cuong Truong

2 replies • 1054 views
Discussion

Can Liberate do characterization for hierarchical SPICE netlist?

Category: Custom IC Design

By dogrush

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updated over 10 years ago by Quek

1 replies • 13845 views
Discussion

not getting parasitic information inside the extracted netlist created using pvs qrc

Category: Custom IC Design

By nads

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updated over 10 years ago by Quek

1 replies • 15093 views
Discussion

how to set up IPVS to use multiple threads

Category: Custom IC Design

By Gaussian

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updated over 10 years ago by Quek

1 replies • 13697 views
Discussion

Has anyone ever ran into a QRC extraction "RC-coupled" with empty .SUBCKT for macro cell

Category: Custom IC Design

By ttran0671

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updated over 10 years ago by Quek

1 replies • 990 views
Discussion

QRC Extraction - Assura

Category: Custom IC Design

By Paolo Minotti

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updated over 10 years ago by Quek

1 replies • 2131 views
Discussion

Simulation of extraced view fails, due to missing supply nets in netlist

Category: Custom IC Design

By marten

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updated over 10 years ago by Quek

1 replies • 13796 views
Discussion

[Solved] MIM capacitor is not being recognized during LVS

Category: Custom IC Design

By Subrata

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updated over 10 years ago by Quek

3 replies • 17861 views
Discussion

Is it possible to run Assura LVS under Ubuntu 14.04?

Category: Custom IC Design

By R Wodnicki

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updated over 10 years ago by Quek

1 replies • 14155 views
Discussion

How do I get Assura to save DRC markers to the layout database like DIVA?

Category: Custom IC Design

By Michael L

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updated over 10 years ago by Quek

1 replies • 14376 views
Discussion

Assura RC deck working in PVS

Category: Custom IC Design

By nads

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updated over 10 years ago by Quek

1 replies • 14534 views
Discussion

Avoid unnecessary large file size in Cadence Transient Simulation

Category: Custom IC Design

By MenghanSun

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updated over 10 years ago by Subrata

1 replies • 15292 views
Discussion

ADEXL: detecting process corners

Category: Custom IC Design

By kawan

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updated over 10 years ago by kawan

6 replies • 17748 views
Discussion

vsource voltage level always 1V, val0 & val1 missing in netlist

Category: Custom IC Design

By marten

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updated over 10 years ago by marten

4 replies • 2132 views

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