Custom IC Design

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vpwlf error: Time is not strictly increasing

Category: Custom IC Design

By surreyian

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updated over 14 years ago by surreyian

6 replies • 21374 views
Discussion

Illogical outputs from cadence (IC5141) ADE.

Category: Custom IC Design

By RAO VINAY

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updated over 14 years ago by RAO VINAY

2 replies • 14466 views
Discussion

How to Find the drawn net("MET1" "drawing") in the layout.

Category: Custom IC Design

By ShrikantTI

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updated over 14 years ago by Andrew Beckett

4 replies • 2957 views
Discussion

Assura LVS: Clarification on virtual connection using joinablePin() function.

Category: Custom IC Design

By ShrikantTI

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updated over 14 years ago by Quek

1 replies • 15861 views
Discussion

effective length variation after Monte Carlo trial

Category: Custom IC Design

By inessadm

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updated over 14 years ago by Andrew Beckett

6 replies • 16690 views
Discussion

Unwanted merge of long transistors in Assura RCX

Category: Custom IC Design

By Ueue

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updated over 14 years ago by Andrew Beckett

1 replies • 14084 views
Discussion

AMS: Grid not seen in Waveforms

Category: Custom IC Design

By medeepak

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updated over 14 years ago by medeepak

2 replies • 14479 views
Discussion

additional properties on layers/instances

Category: Custom IC Design

By lawlag02

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updated over 14 years ago by lawlag02

2 replies • 1134 views
Discussion

Turbo Toolbox Error

Category: Custom IC Design

By mjgoh

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updated over 14 years ago by Quek

3 replies • 15520 views
Discussion

Cadence 6.1.5 ADE question

Category: Custom IC Design

By engine2011

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updated over 14 years ago by Andrew Beckett

2 replies • 14923 views
Discussion

Do license queueing for AMS

Category: Custom IC Design

By RichardCh

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updated over 14 years ago by Andrew Beckett

6 replies • 19561 views
Discussion

save - excluding all signals in a subckt

Category: Custom IC Design

By Wonyoung

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updated over 14 years ago by Wonyoung

2 replies • 2580 views
Discussion

IC6 design tool.

Category: Custom IC Design

By ICredneck

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updated over 14 years ago by ICredneck

7 replies • 15655 views
Discussion

Saving Cadence simulation data for later use

Category: Custom IC Design

By Wonyoung

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updated over 14 years ago by Wonyoung

2 replies • 17187 views
Discussion

VHDLIN producing symbols, not schematics

Category: Custom IC Design

By OOberg

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updated over 14 years ago by Andrew Beckett

1 replies • 14340 views

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