Custom IC Design

Latest Posts

Discussion

how to find total capcitance of mosfet(pmos or nmos)?

Category: Custom IC Design

By pavan261995

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updated over 8 years ago by Andrew Beckett

1 replies • 1050 views
Discussion

anaName in OCEAN analysis not working

Category: Custom IC Design

By leok

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updated over 8 years ago by leok

2 replies • 13889 views
Discussion

QRC extraction problem

Category: Custom IC Design

By umais

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updated over 8 years ago by Andrew Beckett

3 replies • 15620 views
Discussion

Problem saving intrinsic parameters using save statement save NM0:all

Category: Custom IC Design

By Bean1234

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updated over 8 years ago by Andrew Beckett

1 replies • 1836 views
Discussion

Storing config of a cell in a file/cellview

Category: Custom IC Design

By itos

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updated over 8 years ago by Andrew Beckett

3 replies • 2071 views
Discussion

BER test setup in cadence

Category: Custom IC Design

By EngrZM

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started over 8 years ago

0 replies • 13958 views
Discussion

Cadence Virtuoso: Import a large verilog netlist to cadence schematic

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

3 replies • 18972 views
Discussion

layout dynamic selection accessibility?

Category: Custom IC Design

By yeh1

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updated over 8 years ago by Andrew Beckett

1 replies • 13903 views
Discussion

import physical verilog netlist in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

5 replies • 25732 views
Discussion

Assura problems with feedthrough caps

Category: Custom IC Design

By ManuelSuarez

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updated over 8 years ago by ManuelSuarez

2 replies • 14127 views
Discussion

Cadence Liberate: Path delays all zero in exported of verilog models

Category: Custom IC Design

By marten

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updated over 8 years ago by marten

6 replies • 16705 views
Discussion

Spectre: use models on a per module basis?

Category: Custom IC Design

By dontpanic

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updated over 8 years ago by dontpanic

4 replies • 16934 views
Discussion

A few questions regarding using PSS for rectifier design

Category: Custom IC Design

By MenghanSun

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updated over 8 years ago by Andrew Beckett

5 replies • 16443 views
Discussion

Generating a bit stream in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

1 replies • 17262 views
Discussion

Can't open cells in hierarchical schematic in Virtuoso

Category: Custom IC Design

By oAwad

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updated over 8 years ago by Andrew Beckett

1 replies • 3870 views

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