Custom IC Design

Latest Posts

Discussion

How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

Category: Custom IC Design

By iguerra

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updated over 8 years ago by Andrew Beckett

3 replies • 3730 views
Discussion

cds_get_analog_value or cgav is not correct

Category: Custom IC Design

By nthoangga

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updated over 8 years ago by Andrew Beckett

1 replies • 14587 views
Discussion

MDL: create a new waveform and save it into a wavefile

Category: Custom IC Design

By PatrikOsgnach

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updated over 8 years ago by Andrew Beckett

1 replies • 14677 views
Discussion

Monte Carlo analysis with vprbs

Category: Custom IC Design

By Mirco Controller

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updated over 8 years ago by Andrew Beckett

1 replies • 14323 views
Discussion

tdnoise or pnoise?

Category: Custom IC Design

By PeppeW90

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updated over 8 years ago by Andrew Beckett

5 replies • 15790 views
Discussion

Verilog-A model equivalent to primitive model?

Category: Custom IC Design

By greatqs

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updated over 8 years ago by greatqs

3 replies • 16282 views
Discussion

save expression to file in ocean-xl

Category: Custom IC Design

By Karev11

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updated over 8 years ago by Andrew Beckett

1 replies • 14080 views
Discussion

monteCarlo results in percent instead of absolute?

Category: Custom IC Design

By drdanmc

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updated over 8 years ago by Andrew Beckett

2 replies • 14180 views
Discussion

How to see the properties of two cells together which are in same layout window.

Category: Custom IC Design

By conrel

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updated over 8 years ago by Andrew Beckett

1 replies • 14174 views
Discussion

Montecarlo simulation not starting in ADE-XL

Category: Custom IC Design

By saikatc

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updated over 8 years ago by Andrew Beckett

6 replies • 17820 views
Discussion

stitching results of two transient simulations

Category: Custom IC Design

By SoniaMK

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updated over 8 years ago by Andrew Beckett

3 replies • 16123 views
Discussion

missing instance in schematic

Category: Custom IC Design

By SteveRFIC

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updated over 8 years ago by Andrew Beckett

1 replies • 16782 views
Discussion

Need to Set Design before issuing this command

Category: Custom IC Design

By bitan1990

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updated over 8 years ago by Andrew Beckett

1 replies • 14146 views
Discussion

VerilogA Error running Spectre

Category: Custom IC Design

By kevch9988

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updated over 8 years ago by AndreyVolk

2 replies • 14496 views
Discussion

Exporting Horizontal Marker, selecting intercepts by zooming the graph doesn't work

Category: Custom IC Design

By Clidre

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updated over 8 years ago by Frank Wiedmann

1 replies • 2209 views

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