Custom IC Design

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Discussion

ADE L 6.1.4 Parametric/MonteCarlo Sweep

Category: Custom IC Design

By MarkSummers

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updated over 15 years ago by MarkSummers

2 replies • 2616 views
Discussion

ADE plot outputs Cadence5

Category: Custom IC Design

By StreamCX

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updated over 15 years ago by Quek

1 replies • 5334 views
Discussion

ASSURA LVS PROBLEM FOR AMI C5 PDK

Category: Custom IC Design

By CHECKMATE

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updated over 15 years ago by CHECKMATE

6 replies • 16776 views
Discussion

HD2 and HD3 vs Frequency plot

Category: Custom IC Design

By Verdhan

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started over 15 years ago

0 replies • 14511 views
Discussion

Some DRC errors regarding pwell

Category: Custom IC Design

By tester

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updated over 15 years ago by Quek

3 replies • 15346 views
Discussion

Problems with expressions in Monte Carlo

Category: Custom IC Design

By Karo

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updated over 15 years ago by Karo

6 replies • 15789 views
Discussion

Check in Spectre license automatically

Category: Custom IC Design

By archive

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updated over 15 years ago by archive

2 replies • 16356 views
Discussion

how to run the simulaiton for 1 ns step interval ..?

Category: Custom IC Design

By Sunil Kumar K

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updated over 15 years ago by Sunil Kumar K

5 replies • 15507 views
Discussion

Text output on Cadence Composer

Category: Custom IC Design

By archive

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updated over 15 years ago by Andrew Beckett

4 replies • 14581 views
Discussion

creating a matrix of instances in verilog-A

Category: Custom IC Design

By rickrevolta

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updated over 15 years ago by Andrew Beckett

2 replies • 17476 views
Discussion

Pin names

Category: Custom IC Design

By StreamCX

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updated over 15 years ago by Andrew Beckett

7 replies • 11382 views
Discussion

LvsIgnore Properties

Category: Custom IC Design

By frogconsultant

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updated over 15 years ago by frogconsultant

12 replies • 33142 views
Discussion

How to implement this equation in VerilogA

Category: Custom IC Design

By princemahmmod

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updated over 15 years ago by Andrew Beckett

4 replies • 16828 views
Discussion

Cadence 6 waveform error vpwl vsrc

Category: Custom IC Design

By StreamCX

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updated over 15 years ago by StreamCX

9 replies • 9654 views
Discussion

Output SPEF-file from QRC contains only top level ports

Category: Custom IC Design

By Slawa

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updated over 15 years ago by Quek

1 replies • 6280 views

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