Custom IC Design

Latest Posts

Discussion

output setup shows a yellow row

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by sjwprcker

7 replies • 14257 views
Discussion

3-bit flash ADC design

Category: Custom IC Design

By Lohithpras

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updated over 3 years ago by Andrew Beckett

2 replies • 12523 views
Discussion

switch layer when creating a path in 6.1.8?

Category: Custom IC Design

By fireonthesee88

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updated over 3 years ago by Andrew Beckett

1 replies • 9427 views
Discussion

VerilogA End of File

Category: Custom IC Design

By KhanAmir

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started over 3 years ago

0 replies • 8355 views
Discussion

Empty R reporting in Parasitic Backannotation

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 9014 views
Discussion

why schematic and viva trace colors mismatched?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by Andrew Beckett

13 replies • 13842 views
Discussion

SA Register output issue

Category: Custom IC Design

By sounakd01

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started over 3 years ago

0 replies • 8479 views
Discussion

netlist creation issue

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by Andrew Beckett

3 replies • 10165 views
Discussion

Pegasus LVS: how to enforce agreement of fins-per-finger parameter?

Category: Custom IC Design

By dontpanic

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updated over 3 years ago by Andrew Beckett

2 replies • 10478 views
Discussion

How to create auto pin under the cursor select

Category: Custom IC Design

By TonyTang

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updated over 3 years ago by Adam54

6 replies • 10717 views
Discussion

how to trim metal(overhangs over vias)

Category: Custom IC Design

By Nava5495

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started over 3 years ago

0 replies • 1247 views
Discussion

How to change Default Decend View type

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by SpiceMonkey

6 replies • 12816 views
Discussion

Pcells LVS fail. Master not found

Category: Custom IC Design

By RCardella

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started over 3 years ago

0 replies • 8625 views
Discussion

Is there a quicker way to display an output after sims?

Category: Custom IC Design

By kenc184

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updated over 3 years ago by kenc184

3 replies • 9511 views
Discussion

Verilog netlist wont explicit bit connected to bus pin

Category: Custom IC Design

By YB36

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started over 3 years ago

0 replies • 8935 views

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