Custom IC Design

Latest Posts

Discussion

Is it possible to access design variable as parameter of systemverilog bloc

Category: Custom IC Design

By Mathieu Chene

$usertype
•
started over 1 year ago

0 replies • 2709 views
Discussion

Issue OSSPDA with xcellium AMS sim

Category: Custom IC Design

By Binhngo1210

$usertype
•
started over 1 year ago

0 replies • 2675 views
Discussion

Descend menu - Set default preferences

Category: Custom IC Design

By strotta

$usertype
•
updated over 1 year ago by henker

1 replies • 606 views
Discussion

Synchronicity vs maestro view

Category: Custom IC Design

By StephanWeber

$usertype
•
updated over 1 year ago by Andrew Beckett

1 replies • 3064 views
Discussion

Colorcoding for low cpk in Yield-View in Assembler

Category: Custom IC Design

By leok

$usertype
•
updated over 1 year ago by StephanWeber

1 replies • 3404 views
Discussion

ADE output for conditional string from input logic combination

Category: Custom IC Design

By StephanWeber

$usertype
•
started over 1 year ago

0 replies • 2643 views
Discussion

back annotating bussed terminal DC voltages with cdsterm in Symbol

Category: Custom IC Design

By ebecheto

$usertype
•
updated over 1 year ago by ebecheto

4 replies • 3479 views
Discussion

Unable to run PVS Quantus extraction in cds_ff_mpt (finfet 18nm)

Category: Custom IC Design

By nikhil2798gp

$usertype
•
updated over 1 year ago by Ganesh

6 replies • 4144 views
Discussion

Characterizing cells with verilog-A models by liberate, but the model or instance can not be found

Category: Custom IC Design

By RL202501168650

$usertype
•
updated over 1 year ago by Guangjun Cao

7 replies • 5456 views
Discussion

how to start virtuoso with multi-core(cpu)?

Category: Custom IC Design

By Yush

$usertype
•
updated over 1 year ago by Andrew Beckett

1 replies • 837 views
Discussion

Transient Analysis Terminated without error message

Category: Custom IC Design

By JK20250114453

$usertype
•
updated over 1 year ago by Andrew Beckett

1 replies • 2932 views
Discussion

Export assembler measurement to vcsv files

Category: Custom IC Design

By TH20240912844

$usertype
•
updated over 1 year ago by TH20240912844

2 replies • 3181 views
Discussion

How to use the array index to parametrize the delay

Category: Custom IC Design

By Svilen64

$usertype
•
updated over 1 year ago by Andrew Beckett

1 replies • 2803 views
Discussion

Selecting all same cells in layout

Category: Custom IC Design

By TobyK

$usertype
•
updated over 1 year ago by TobyK

3 replies • 3224 views
Discussion

ADE Assembler Outputs Setup: Automatically save all nets included in expr rows

Category: Custom IC Design

By brianbranch

$usertype
•
started over 1 year ago

0 replies • 2714 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.