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Custom IC Design

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  • Discussion

    Error during the RC extraction using 45 nm technology

    Category: Custom IC Design

    By vinod joshi

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 14005 views
  • Discussion

    lineread command error out when trying to read a verilog generation log file

    Category: Custom IC Design

    By mlea

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 14140 views
  • Discussion

    Pass Path and Filename via Variable in ADEXL

    Category: Custom IC Design

    By SebastianS

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    •

    started over 9 years ago

    0 replies • 15416 views
  • Discussion

    "FATAL: Insufficient memory available" spectre issue

    Category: Custom IC Design

    By Dresdener

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    •

    updated over 9 years ago by Dresdener

    2 replies • 6789 views
  • Discussion

    Help with Verilog-A file operation tasks

    Category: Custom IC Design

    By Reks

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 15067 views
  • Discussion

    Sweep vth values

    Category: Custom IC Design

    By syafiq

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    •

    updated over 9 years ago by Andrew Beckett

    4 replies • 14716 views
  • Discussion

    preferred way to sweep temperature in ADEXL

    Category: Custom IC Design

    By danmc91

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    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 22518 views
  • Discussion

    Oscillator frequency discrepancy between PSS and transient simulation

    Category: Custom IC Design

    By Juanelin

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    •

    updated over 9 years ago by Juanelin

    2 replies • 15830 views
  • Discussion

    need help to scale mosaic or instances

    Category: Custom IC Design

    By imaneet

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    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 15187 views
  • Discussion

    Automate exporting ADE XL scalar outputs across History

    Category: Custom IC Design

    By Michele Ancis

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    •

    started over 9 years ago

    0 replies • 13566 views
  • Discussion

    Selected net in Navigator: Is it possible to change default selected net color of white?

    Category: Custom IC Design

    By ShawnLogan

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    •

    started over 9 years ago

    0 replies • 12318 views
  • Discussion

    Integration band for Noise type "timeaverage" Vs "jitter" method in pnoise analysis?

    Category: Custom IC Design

    By suresh naidu

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    •

    started over 9 years ago

    0 replies • 1547 views
  • Discussion

    iPDK from TSMC 28nm pcell problems

    Category: Custom IC Design

    By Luc Laeveren

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    •

    updated over 9 years ago by Quek

    7 replies • 20770 views
  • Discussion

    ADE XL : How to sort results when running corner simulation ?

    Category: Custom IC Design

    By scaduc

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    •

    started over 9 years ago

    0 replies • 13789 views
  • Discussion

    *Error* Library "my_lib" does not exist

    Category: Custom IC Design

    By Michele Ancis

    $usertype

    •

    updated over 9 years ago by Michele Ancis

    2 replies • 4606 views
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