Custom IC Design

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Interactive verilogA models in Spectre

Category: Custom IC Design

By Sali

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updated over 11 years ago by Sali

2 replies • 13986 views
Discussion

How to create a final netlist from ADE-XL with global variables using Skill?

Category: Custom IC Design

By adeuser777

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updated over 11 years ago by sram8t

7 replies • 18282 views
Discussion

How to Queue for a Virtuoso Schematic Editor License

Category: Custom IC Design

By nbyrne

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updated over 11 years ago by Andrew Beckett

4 replies • 15586 views
Discussion

Installing and setting up PVS10.1.2 on IC6.15

Category: Custom IC Design

By Alex Vasjanov

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updated over 11 years ago by Andrew Beckett

1 replies • 15423 views
Discussion

waveform processing question in Virtuoso ViVA

Category: Custom IC Design

By apple419

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updated over 11 years ago by Tawna

4 replies • 16256 views
Discussion

Wierd selection option

Category: Custom IC Design

By alpine

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updated over 11 years ago by alpine

2 replies • 13637 views
Discussion

finding usage/references/instances of a cell in same/other libraries Virtuoso IC6.1.4.500.12

Category: Custom IC Design

By tdtg

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updated over 11 years ago by Andrew Beckett

2 replies • 4165 views
Discussion

Xdefault for LSW menu text

Category: Custom IC Design

By danmc

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updated over 11 years ago by danmc

4 replies • 14747 views
Discussion

Verilog-A read file separated by delays

Category: Custom IC Design

By kennethbrun

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updated over 11 years ago by Andrew Beckett

12 replies • 23881 views
Discussion

Report the netlist types used in ADE XL netlists?

Category: Custom IC Design

By sram8t

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updated over 11 years ago by sram8t

9 replies • 16110 views
Discussion

Execution of ocean script in Cadence IC 6.1.5 and Cadence IC 5.1.41

Category: Custom IC Design

By Lings

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updated over 11 years ago by Andrew Beckett

5 replies • 15476 views
Discussion

Layout GXL: Flight wires not displaying

Category: Custom IC Design

By wewa

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updated over 11 years ago by wewa

4 replies • 16835 views
Discussion

How to execute a c programme in UNIX using SKILL

Category: Custom IC Design

By AmitBiswas

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updated over 11 years ago by Andrew Beckett

1 replies • 13954 views
Discussion

VerilogA models in Cadence

Category: Custom IC Design

By Sali

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updated over 11 years ago by Sali

12 replies • 23100 views
Discussion

LVS does not accept proper termOrder

Category: Custom IC Design

By Kabal

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updated over 11 years ago by Kabal

9 replies • 20567 views

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