Custom IC Design

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Discussion

Generate layout from symbols with design variables

Category: Custom IC Design

By James Yam

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updated over 3 years ago by James Yam

2 replies • 10250 views
Discussion

QRC Configuration options in PVS

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

4 replies • 10614 views
Discussion

Use instance name for design variable in schematic

Category: Custom IC Design

By ZipppyDoctor

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started over 3 years ago

0 replies • 8613 views
Discussion

Calculator: How to avoid interpolation when using spectrumMeasurement()?

Category: Custom IC Design

By jorgeluislagos

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updated over 3 years ago by jorgeluislagos

4 replies • 10845 views
Discussion

Is there any documentation for PVS DRC rules writting?

Category: Custom IC Design

By delgsy

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updated over 3 years ago by delgsy

2 replies • 10803 views
Discussion

replace square bus notation brackets with < and >

Category: Custom IC Design

By pula58

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updated over 3 years ago by shubhamiitb

1 replies • 3174 views
Discussion

I am trying to simulate a basic ring oscillator circuit using spectra . I have generated a netlist file. when I run it, I am getting the following error: I need help urgently for my thesis

Category: Custom IC Design

By Sudipta

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updated over 3 years ago by Andrew Beckett

1 replies • 9596 views
Discussion

follow up with find the location of a variable in schematic

Category: Custom IC Design

By monglebest2022

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updated over 3 years ago by Andrew Beckett

1 replies • 9442 views
Discussion

How to change default spacing between symbol's pins that auto-created from schematic

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by Andrew Beckett

1 replies • 1876 views
Discussion

DEF formatting

Category: Custom IC Design

By SSR

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updated over 3 years ago by SSR

1 replies • 9246 views
Discussion

Discrepancy in Stability Analysis

Category: Custom IC Design

By Ashish Papreja

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updated over 3 years ago by FormerMember

1 replies • 9720 views
Discussion

adding delay element to circuit

Category: Custom IC Design

By Soly

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updated over 3 years ago by FormerMember

1 replies • 13246 views
Discussion

calculator plot function fail

Category: Custom IC Design

By sjwprcker

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updated over 3 years ago by FormerMember

1 replies • 9389 views
Discussion

SystemVerilog generate loop does not compile modules defined inside loop

Category: Custom IC Design

By Nader Fathy

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updated over 3 years ago by SimbaG

2 replies • 12544 views
Discussion

Dc level shifter

Category: Custom IC Design

By Khaleed01

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updated over 3 years ago by FormerMember

3 replies • 11355 views

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