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Custom IC Design

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  • Discussion

    Standard Cell Libraries (Basic)

    Category: Custom IC Design

    By AndreyVolk

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    updated over 8 years ago by AndreyVolk

    2 replies • 6491 views
  • Discussion

    Phase Margin Calculation

    Category: Custom IC Design

    By netbug

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    updated over 8 years ago by Andrew Beckett

    1 replies • 16945 views
  • Discussion

    Error running DRC on Assura - "The Assura DRC Run Failed"

    Category: Custom IC Design

    By fanelli

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    updated over 8 years ago by fanelli

    2 replies • 2736 views
  • Discussion

    creating custom cell

    Category: Custom IC Design

    By asetji

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    •

    started over 8 years ago

    0 replies • 13969 views
  • Discussion

    problem simulating a sub-circuit (spectre model) with ade

    Category: Custom IC Design

    By asetji

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    updated over 8 years ago by asetji

    3 replies • 16064 views
  • Discussion

    VerilogA vs. built-in device models

    Category: Custom IC Design

    By samer1

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    updated over 8 years ago by samer1

    2 replies • 14160 views
  • Discussion

    How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

    Category: Custom IC Design

    By iguerra

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    updated over 8 years ago by Andrew Beckett

    3 replies • 3658 views
  • Discussion

    cds_get_analog_value or cgav is not correct

    Category: Custom IC Design

    By nthoangga

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14454 views
  • Discussion

    MDL: create a new waveform and save it into a wavefile

    Category: Custom IC Design

    By PatrikOsgnach

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14523 views
  • Discussion

    Monte Carlo analysis with vprbs

    Category: Custom IC Design

    By Mirco Controller

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 14168 views
  • Discussion

    tdnoise or pnoise?

    Category: Custom IC Design

    By PeppeW90

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    updated over 8 years ago by Andrew Beckett

    5 replies • 15621 views
  • Discussion

    Verilog-A model equivalent to primitive model?

    Category: Custom IC Design

    By greatqs

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    updated over 8 years ago by greatqs

    3 replies • 16112 views
  • Discussion

    save expression to file in ocean-xl

    Category: Custom IC Design

    By Karev11

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    updated over 8 years ago by Andrew Beckett

    1 replies • 13937 views
  • Discussion

    monteCarlo results in percent instead of absolute?

    Category: Custom IC Design

    By drdanmc

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    updated over 8 years ago by Andrew Beckett

    2 replies • 14028 views
  • Discussion

    How to see the properties of two cells together which are in same layout window.

    Category: Custom IC Design

    By conrel

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 14014 views
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