Custom IC Design

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Discussion

LvsIgnore Properties

Category: Custom IC Design

By frogconsultant

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updated over 15 years ago by frogconsultant

12 replies • 33589 views
Discussion

How to implement this equation in VerilogA

Category: Custom IC Design

By princemahmmod

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updated over 15 years ago by Andrew Beckett

4 replies • 17029 views
Discussion

Cadence 6 waveform error vpwl vsrc

Category: Custom IC Design

By StreamCX

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updated over 15 years ago by StreamCX

9 replies • 9755 views
Discussion

Output SPEF-file from QRC contains only top level ports

Category: Custom IC Design

By Slawa

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updated over 15 years ago by Quek

1 replies • 6307 views
Discussion

Off-Grid pins warning in abstract generation

Category: Custom IC Design

By affaq

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updated over 15 years ago by Alex Soyer

3 replies • 15048 views
Discussion

subciruit initiated top-level current probe

Category: Custom IC Design

By Kalimero

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updated over 15 years ago by Kalimero

5 replies • 17885 views
Discussion

cadence verilog ams environment setup question

Category: Custom IC Design

By Wing2

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updated over 15 years ago by EricCDN

1 replies • 19636 views
Discussion

How to short small resistor for lvs purpose

Category: Custom IC Design

By harleyMax

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updated over 15 years ago by Andrew Beckett

7 replies • 20955 views
Discussion

Manual editing of a p2lvsfile

Category: Custom IC Design

By Slawa

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updated over 15 years ago by Slawa

6 replies • 7955 views
Discussion

How to change the Internal Cell names

Category: Custom IC Design

By sathisha

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updated over 15 years ago by Quek

1 replies • 15680 views
Discussion

ASSURA41-614: ERROR rcAddRegionTasks

Category: Custom IC Design

By tkhan

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updated over 15 years ago by Andrew Beckett

3 replies • 14538 views
Discussion

How to add PVS menu in virtuoso layout editor

Category: Custom IC Design

By shushan

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updated over 15 years ago by shushan

2 replies • 15517 views
Discussion

dose anyone know how to solve this problem???

Category: Custom IC Design

By Jay12

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updated over 15 years ago by Andrew Beckett

1 replies • 13947 views
Discussion

custum mdl functions in assertions

Category: Custom IC Design

By MarkSummers

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updated over 15 years ago by Andrew Beckett

1 replies • 14166 views
Discussion

Anyone used EQN(..) in Virtuoso-ADE->Setup Outputs?

Category: Custom IC Design

By swdesigner

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updated over 15 years ago by Andrew Beckett

2 replies • 860 views

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