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Custom IC Design

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  • Discussion

    malias function

    Category: Custom IC Design

    By VINCENTCHENG

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    updated over 6 years ago by Andrew Beckett

    3 replies • 15549 views
  • Discussion

    CADENCE IC STUDENT VERSION/TRIAL VERSION

    Category: Custom IC Design

    By Thorin

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    updated over 6 years ago by Anton Klotz

    6 replies • 21999 views
  • Discussion

    Cannot EDIF out

    Category: Custom IC Design

    By Kevinholo

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    •

    updated over 6 years ago by yankunRen

    3 replies • 15135 views
  • Discussion

    Set Subwindow ID for each Trace / Waveform

    Category: Custom IC Design

    By ChristophIMS

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 14161 views
  • Discussion

    How to set a custom via as default via on VXL/GXL?

    Category: Custom IC Design

    By Tom Sawyer

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    •

    updated over 6 years ago by Vallabhamj

    1 replies • 1371 views
  • Discussion

    Small signal analysis during transient, triggered by event

    Category: Custom IC Design

    By StevenMikes

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    •

    updated over 6 years ago by StevenMikes

    6 replies • 17854 views
  • Discussion

    ADE L simulation gave error!

    Category: Custom IC Design

    By ennng

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    •

    updated over 6 years ago by Andrew Beckett

    6 replies • 17837 views
  • Discussion

    Renaming multiple wires using wildcard

    Category: Custom IC Design

    By GDCRA

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 15604 views
  • Discussion

    Does saving more number of nets increase simulation time

    Category: Custom IC Design

    By PrasadAMSEng

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    updated over 6 years ago by Andrew Beckett

    1 replies • 13992 views
  • Discussion

    Spectre assert output message - printing a variable

    Category: Custom IC Design

    By Shico90

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    •

    updated over 6 years ago by Frank Wiedmann

    3 replies • 2265 views
  • Discussion

    How to get a free student copy of NC Verilog Simulator

    Category: Custom IC Design

    By laddu0

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    updated over 6 years ago by StefanAlbrecht

    8 replies • 22378 views
  • Discussion

    Cadence Calibre LVS Error with missing connection.

    Category: Custom IC Design

    By Jeffren

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    •

    updated over 6 years ago by Andrew Beckett

    1 replies • 16982 views
  • Discussion

    spectre captab: 1) negative capacitance 2) not reciprocal values

    Category: Custom IC Design

    By ZoltanT

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    updated over 6 years ago by ZoltanT

    4 replies • 17964 views
  • Discussion

    save and restart in ams simulator

    Category: Custom IC Design

    By nnlt

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    •

    updated over 6 years ago by Praveenvenk19

    2 replies • 15814 views
  • Discussion

    stimulus test bench

    Category: Custom IC Design

    By jyoti kandpal

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    •

    updated over 6 years ago by FormerMember

    1 replies • 14571 views
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