Custom IC Design

Latest Posts

Discussion

Is there any way to use assura compatible file (*.drc , *.lvs ) file in PVS plugin (*.pvl)

Category: Custom IC Design

By Anklon

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14801 views
Discussion

ADE L error

Category: Custom IC Design

By Anklon

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 16958 views
Discussion

Environment variable to prevent "stream in translation complete" pop up dialogue after streamout and streamin

Category: Custom IC Design

By blankman

$usertype
•
updated over 8 years ago by blankman

2 replies • 1276 views
Discussion

How to plot transistor's parameters evolution over time with transient simulation

Category: Custom IC Design

By Edouard R

$usertype
•
updated over 8 years ago by Edouard R

3 replies • 5800 views
Discussion

PEX Compilation Error

Category: Custom IC Design

By mehdina94rm

$usertype
•
updated over 8 years ago by marten

2 replies • 16380 views
Discussion

How to fix warning from Spectre about a missing bulk-source and bulk-drain diode?

Category: Custom IC Design

By Bean Nakamura

$usertype
•
updated over 8 years ago by taraRF

3 replies • 16413 views
Discussion

installation issue in Installscape through DVD

Category: Custom IC Design

By conrel

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 14585 views
Discussion

" *Error* asiGetDesignLibName: no applicable method for the class - list" during parametric simulation in ADE

Category: Custom IC Design

By yayla

$usertype
•
updated over 8 years ago by Andrew Beckett

6 replies • 5960 views
Discussion

Convergence difficulties in Verilog A while using equivalent differential equation instead of laplace_nd function

Category: Custom IC Design

By Quilon

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 16324 views
Discussion

Virtuoso Layout XL/GXL -- rasterizing an anyAngle polygon onto a grid

Category: Custom IC Design

By jack.holloway

$usertype
•
updated over 8 years ago by MarkRuiter

2 replies • 3315 views
Discussion

CDS_thru, LVS, new layer

Category: Custom IC Design

By samer1

$usertype
•
updated over 8 years ago by samer1

3 replies • 15677 views
Discussion

varying inline subckt parameter with altergroup in Spectre

Category: Custom IC Design

By sunilm123

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 15785 views
Discussion

$system() command in Verilog-A

Category: Custom IC Design

By farhan89

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 15043 views
Discussion

PDK menu not showing in CIW

Category: Custom IC Design

By wgtkan

$usertype
•
updated over 8 years ago by Andrew Beckett

1 replies • 15623 views
Discussion

ADE simulation setup toolbar missing buttons

Category: Custom IC Design

By wgtkan

$usertype
•
updated over 8 years ago by Andrew Beckett

3 replies • 15928 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

Custom IC Design

Latest Posts

Is there any way to use assura compatible file (.drc , .lvs ) file in PVS plugin (*.pvl)

ADE L error

Environment variable to prevent "stream in translation complete" pop up dialogue after streamout and streamin

How to plot transistor's parameters evolution over time with transient simulation

PEX Compilation Error

How to fix warning from Spectre about a missing bulk-source and bulk-drain diode?

installation issue in Installscape through DVD

" Error asiGetDesignLibName: no applicable method for the class - list" during parametric simulation in ADE

Convergence difficulties in Verilog A while using equivalent differential equation instead of laplace_nd function

Virtuoso Layout XL/GXL -- rasterizing an anyAngle polygon onto a grid

CDS_thru, LVS, new layer

varying inline subckt parameter with altergroup in Spectre

$system() command in Verilog-A

PDK menu not showing in CIW

ADE simulation setup toolbar missing buttons

Community Guidelines