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Custom IC Design

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  • Discussion

    Using SPICE level 3 MOSFET model in SPECTRE

    Category: Custom IC Design

    By keensport keensport

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 15729 views
  • Discussion

    ic5141 value stack (second) over flow problem

    Category: Custom IC Design

    By rockyman rockyman

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 12952 views
  • Discussion

    standard cell design

    Category: Custom IC Design

    By RajawatMANIT RajawatMANIT

    •

    started over 9 years ago

    0 replies • 12657 views
  • Discussion

    Interconnect reliability

    Category: Custom IC Design

    By rafaelon rafaelon

    •

    updated over 9 years ago by Andrew Beckett

    1 replies • 12892 views
  • Discussion

    ADE windowID for a given sevSession?

    Category: Custom IC Design

    By yeh1 yeh1

    •

    updated over 9 years ago by Andrew Beckett

    3 replies • 13371 views
  • Discussion

    CDL generation with command si: how to specify a path instead of "netlist" for the resultFile ?

    Category: Custom IC Design

    By samung samung

    •

    updated over 9 years ago by samung

    2 replies • 3785 views
  • Discussion

    psub and nwell via not present in 90nm layout

    Category: Custom IC Design

    By PS90 PS90

    •

    updated over 9 years ago by ColinSutlieff

    1 replies • 13608 views
  • Discussion

    Display Issue in IC6.1.6 (64 bit) on CentOS

    Category: Custom IC Design

    By Raghu Rao Raghu Rao

    •

    updated over 9 years ago by Andrew Beckett

    2 replies • 13577 views
  • Discussion

    simulation a circuit with organic transistors

    Category: Custom IC Design

    By robert11 robert11

    •

    updated over 9 years ago by ArchAngelos

    4 replies • 13843 views
  • Discussion

    AMS netlisting has failed

    Category: Custom IC Design

    By elfmushroom elfmushroom

    •

    updated over 9 years ago by elfmushroom

    2 replies • 17011 views
  • Discussion

    Liberate (pass/file bisection)

    Category: Custom IC Design

    By kasula5 kasula5

    •

    started over 9 years ago

    0 replies • 448 views
  • Discussion

    Printed OFET PDK Development

    Category: Custom IC Design

    By ramkumarg ramkumarg

    •

    updated over 9 years ago by robert11

    2 replies • 12832 views
  • Discussion

    Changing default settings of Virtuoso Layout XL

    Category: Custom IC Design

    By Clidre Clidre

    •

    updated over 9 years ago by Clidre

    2 replies • 17714 views
  • Discussion

    How to fix layers after changing layer numbers in the technology file

    Category: Custom IC Design

    By Sheppy Sheppy

    •

    updated over 9 years ago by theopaone

    5 replies • 17035 views
  • Discussion

    how to attach a new device file in cadence virtuoso version 6.1.2

    Category: Custom IC Design

    By RAVI2100 RAVI2100

    •

    updated over 9 years ago by Quek

    1 replies • 13189 views
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