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Custom IC Design

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  • Discussion

    Problem in creating logic to electrical connect module in verilogams

    Category: Custom IC Design

    By indra0804

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    started over 12 years ago

    0 replies • 15235 views
  • Discussion

    Problem while running verilog-ams block in cadence schematic editor

    Category: Custom IC Design

    By indra0804

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    •

    updated over 12 years ago by indra0804

    2 replies • 16122 views
  • Discussion

    Initial condition in subcircuit

    Category: Custom IC Design

    By MaK78

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    updated over 12 years ago by MaK78

    3 replies • 17757 views
  • Discussion

    Charge Pump output Capacitance

    Category: Custom IC Design

    By Mushir

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    updated over 12 years ago by Andrew Beckett

    8 replies • 17814 views
  • Discussion

    How to resolve xstreamout (IC 6.1) , it pop you to save cellview ?

    Category: Custom IC Design

    By Charley Chen

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    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 14132 views
  • Discussion

    DC sweep with ams simulator ?

    Category: Custom IC Design

    By isazulkc

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    updated over 12 years ago by isazulkc

    2 replies • 14257 views
  • Discussion

    ELC problem: simulation failed with the status 512

    Category: Custom IC Design

    By Digital84

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    updated over 12 years ago by Digital84

    2 replies • 14320 views
  • Discussion

    How to use frequency in calculator when doing AC Sweep in Virtuoso

    Category: Custom IC Design

    By nonlocality

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    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 26298 views
  • Discussion

    How to change analysis type in Ocean?

    Category: Custom IC Design

    By Honghao

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    •

    updated over 12 years ago by Honghao

    2 replies • 14557 views
  • Discussion

    IC61 Custom Digital Placer skill for rows calculation

    Category: Custom IC Design

    By Eduard Raines

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    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 13903 views
  • Discussion

    Ultrasim is not recognising hspice (<) syntax

    Category: Custom IC Design

    By Ankumar15

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    updated over 12 years ago by Andrew Beckett

    1 replies • 1050 views
  • Discussion

    Any way to use ADE variables in Hierarchy Editor ?

    Category: Custom IC Design

    By kentauta

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    updated over 12 years ago by kentauta

    2 replies • 14289 views
  • Discussion

    utsoi model for spectre?

    Category: Custom IC Design

    By huber

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    •

    updated over 12 years ago by huber

    2 replies • 13976 views
  • Discussion

    Opening layout view opens schematic view

    Category: Custom IC Design

    By egolowen

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    •

    updated over 12 years ago by Andrew Beckett

    3 replies • 15239 views
  • Discussion

    How to plot the verilogA module data points using OCEAN

    Category: Custom IC Design

    By RFStuff

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    •

    updated over 12 years ago by Andrew Beckett

    9 replies • 16950 views
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