Custom IC Design

Latest Posts

Discussion

OCEAN script generated for AMS + APS simulation

Category: Custom IC Design

By alleyor

$usertype
•
updated over 12 years ago by Andrew Beckett

2 replies • 14714 views
Discussion

meassuring delay in viva

Category: Custom IC Design

By jerry124

$usertype
•
updated over 12 years ago by Andrew Beckett

3 replies • 15922 views
Discussion

Power net short error during Verilog import

Category: Custom IC Design

By Kabal

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 15366 views
Discussion

Error with Assura QRC using IBM 0.13um SiGe

Category: Custom IC Design

By sriram123

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 14006 views
Discussion

Monte carlo pre-run script

Category: Custom IC Design

By LinuxMachine

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 14730 views
Discussion

Transistor Finger/Multiplier does not work

Category: Custom IC Design

By EricHsu

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 2226 views
Discussion

Capacitor Mismatch Coefficient for gpdk 180nm technology

Category: Custom IC Design

By indra0804

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 14988 views
Discussion

CMRR of an OP amp

Category: Custom IC Design

By kenambo

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 16377 views
Discussion

Veriloga Montecarlo input from spectre

Category: Custom IC Design

By jeffreyprin

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 13665 views
Discussion

Monte carlo on a verilog A custom macro model based on device instance not subckt instance

Category: Custom IC Design

By Fabb

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 15090 views
Discussion

How do I turn off flighlines from the bulk of transistors....

Category: Custom IC Design

By pham777

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 13526 views
Discussion

Component Display parameter missing in EDIT menu Cadence 6.1.6-64b

Category: Custom IC Design

By sasuke

$usertype
•
updated over 12 years ago by Marc Heise

1 replies • 16200 views
Discussion

Pins, Nets created are not visible

Category: Custom IC Design

By Prash123

$usertype
•
updated over 12 years ago by Andrew Beckett

1 replies • 14247 views
Discussion

Timestamp.....

Category: Custom IC Design

By pham777

$usertype
•
updated over 12 years ago by aflex

2 replies • 13802 views
Discussion

Reading a data file in Veriloga code

Category: Custom IC Design

By Sali

$usertype
•
updated over 12 years ago by Sali

4 replies • 18009 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.