Custom IC Design

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Discussion

How do I control CDLIn generating User Property information?

Category: Custom IC Design

By Amanda2

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updated over 14 years ago by Amanda2

6 replies • 14918 views
Discussion

IIP3 and NF measurements in cadence spectre for Fully Differential Active-RC Filter

Category: Custom IC Design

By jimito13

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started over 14 years ago

0 replies • 13159 views
Discussion

deselect when zoom to unconnected net?

Category: Custom IC Design

By linbo

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updated over 14 years ago by linbo

2 replies • 13199 views
Discussion

viewing the simulation results with viewer in cadence

Category: Custom IC Design

By Hazo

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updated over 14 years ago by Andrew Beckett

1 replies • 13462 views
Discussion

turning off VXL connectivity in non VXL context

Category: Custom IC Design

By linbo

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updated over 14 years ago by Andrew Beckett

1 replies • 13119 views
Discussion

Simulation with MATLAB generated data file as input to Anagol block

Category: Custom IC Design

By Analog Design

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updated over 14 years ago by Andrew Beckett

3 replies • 13889 views
Discussion

About function define

Category: Custom IC Design

By bobbygang

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updated over 14 years ago by bobbygang

6 replies • 15233 views
Discussion

turning off Illegal Weak-Connect check in VXL

Category: Custom IC Design

By linbo

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updated over 14 years ago by Quek

1 replies • 14735 views
Discussion

Abstract Generator Crash!!

Category: Custom IC Design

By eklikeroomys

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updated over 14 years ago by Andrew Beckett

3 replies • 13632 views
Discussion

Rulers as Objects

Category: Custom IC Design

By Apes

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updated over 14 years ago by Andrew Beckett

4 replies • 14347 views
Discussion

Command openResults problem

Category: Custom IC Design

By loon

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updated over 14 years ago by Andrew Beckett

1 replies • 13289 views
Discussion

Regarding behavioural modelling of analog design

Category: Custom IC Design

By Analog Design

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updated over 14 years ago by Analog Design

2 replies • 13291 views
Discussion

hiSubEventShell() what is that?

Category: Custom IC Design

By fomin

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updated over 14 years ago by skillUser

1 replies • 13132 views
Discussion

How to plot my own data in cadence

Category: Custom IC Design

By loon

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updated over 14 years ago by loon

3 replies • 15852 views
Discussion

How to do analog modeling with verilog -A

Category: Custom IC Design

By Analog Design

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updated over 14 years ago by Andrew Beckett

1 replies • 540 views

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