Custom IC Design

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AGPDK cds_ff_mpt_v_1.0

Category: Custom IC Design

By Vamshi S K

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updated over 4 years ago by Andrew Beckett

1 replies • 10789 views
Discussion

Generating .lib file for synthesis using Genus from transistor level cells using Virtuoso

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by Guangjun Cao

28 replies • 33079 views
Discussion

compare two netlists

Category: Custom IC Design

By sjwprcker

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updated over 4 years ago by MaximX

3 replies • 15828 views
Discussion

Assura doesn't recognise pins generated from sources

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by iamKarthikBK

5 replies • 2979 views
Discussion

[ Liberate ] Cells do not have -extsim_model parameter specified in define_leafcell command

Category: Custom IC Design

By iamKarthikBK

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updated over 4 years ago by iamKarthikBK

34 replies • 21615 views
Discussion

error in plotting Y vs Y

Category: Custom IC Design

By mmsaad66

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updated over 4 years ago by Andrew Beckett

3 replies • 11826 views
Discussion

license to run spectre electro-thermal demo

Category: Custom IC Design

By jjwwlin

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updated over 4 years ago by Andrew Beckett

3 replies • 12308 views
Discussion

Transient noise noise_fmax vs. sampling rate

Category: Custom IC Design

By Jere Jarvinen

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updated over 4 years ago by Jere Jarvinen

2 replies • 12431 views
Discussion

What is the meaning of the parent purpose in a LPP?

Category: Custom IC Design

By RVERP

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updated over 4 years ago by RVERP

2 replies • 11634 views
Discussion

How can I get tabular data of I-V current

Category: Custom IC Design

By yysunj

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updated over 4 years ago by Andrew Beckett

1 replies • 10576 views
Discussion

real-time tuning simulation with transient

Category: Custom IC Design

By threepwood06

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updated over 4 years ago by threepwood06

8 replies • 13995 views
Discussion

SpectreMDL sensitivity analysis

Category: Custom IC Design

By mihaiciortuz

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updated over 4 years ago by mihaiciortuz

8 replies • 14941 views
Discussion

Update global variables from active setup to run plan

Category: Custom IC Design

By rod1

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updated over 4 years ago by rod1

3 replies • 12921 views
Discussion

Run plan for running a single test with different variables each time

Category: Custom IC Design

By Ernesto1

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updated over 4 years ago by rod1

3 replies • 13009 views
Discussion

Copied adexl view have a reference to original view's history paths in data.sdb

Category: Custom IC Design

By PatrikOsgnach

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updated over 4 years ago by Danielrayray

6 replies • 4327 views

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