Custom IC Design

Latest Posts

Discussion

Testbench for THD and IIP3 simulations

Category: Custom IC Design

By Hossein Eslahi

$usertype
•
updated over 3 years ago by FormerMember

5 replies • 12310 views
Discussion

Use if statement to define parameters in Monte Carlo simulation

Category: Custom IC Design

By Holz

$usertype
•
updated over 3 years ago by Andrew Beckett

7 replies • 13295 views
Discussion

Run Options of ADE Assembler in Cadence Virtuoso

Category: Custom IC Design

By Senan

$usertype
•
updated over 3 years ago by Senan

6 replies • 14510 views
Discussion

Virtuoso License Issue: status code -5.

Category: Custom IC Design

By Paulo Aguirre

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 3913 views
Discussion

Maestro - Elapsed time to results

Category: Custom IC Design

By JeyJey

$usertype
•
updated over 3 years ago by FormerMember

11 replies • 6056 views
Discussion

illegal weak connection warning issue

Category: Custom IC Design

By Senan

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 13462 views
Discussion

question ： standard cell symbol import to virtuoso

Category: Custom IC Design

By jackkong

$usertype
•
updated over 3 years ago by jackkong

10 replies • 13837 views
Discussion

$analog_node_alias() usage with vector nets

Category: Custom IC Design

By dtodorov

$usertype
•
updated over 3 years ago by dtodorov

1 replies • 9782 views
Discussion

Exporting device component values and operating conditions into a table in Virtuoso

Category: Custom IC Design

By sidm

$usertype
•
updated over 3 years ago by FormerMember

3 replies • 10825 views
Discussion

constrain the memory use in cadence

Category: Custom IC Design

By huadel

$usertype
•
updated over 3 years ago by SC6789

3 replies • 16963 views
Discussion

Control flow when a return from an expression is nil

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by FormerMember

4 replies • 11975 views
Discussion

Any efficient way to do calibration using calcVal and MonteCarlo for tripple nested loop?

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by delgsy

2 replies • 10403 views
Discussion

DC Convergence Problem When Simulating a Post-Layout r_c and r_c_cc Extraction

Category: Custom IC Design

By shbmsra12

$usertype
•
updated over 3 years ago by Andrew Beckett

5 replies • 12623 views
Discussion

xi0.m1: Effective length is less than or equal to zero?? newbie in cadence!

Category: Custom IC Design

By archive

$usertype
•
updated over 3 years ago by Andrew Beckett

4 replies • 17277 views
Discussion

leaf cell issue with using diffstbprobe

Category: Custom IC Design

By kenc184

$usertype
•
updated over 3 years ago by kenc184

2 replies • 11182 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.