Custom IC Design

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Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett

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started over 14 years ago

0 replies • 29609 views
Discussion

Question on integrated noise in PNOISE (sampled) Noise summary

Category: Custom IC Design

By Yuto Lau

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updated 2 hours ago by Yuto Lau

4 replies • 131 views
Discussion

copy of a maestro view and chnaging design cause all the setup to be lost

Category: Custom IC Design

By TommasoF

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updated 6 hours ago by TommasoF

2 replies • 68 views
Discussion

Automating Layout Cell Updates Using SKILL with Cell List from File

Category: Custom IC Design

By AR202509246930

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updated 6 hours ago by Andrew Beckett

1 replies • 56 views
Discussion

plotting results does not properly work

Category: Custom IC Design

By TommasoF

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updated 10 hours ago by TommasoF

8 replies • 338 views
Discussion

Issue with Skywater 130 Monte Carlo Mismatch Analysis

Category: Custom IC Design

By VLSI lab IITB

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updated 11 hours ago by Andrew Beckett

4 replies • 495 views
Discussion

Query regarding Virtuoso EMX tool

Category: Custom IC Design

By VLSI lab IITB

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updated 13 hours ago by VLSI lab IITB

4 replies • 308 views
Discussion

about cadence virtuoso guidance manual problem

Category: Custom IC Design

By JJ202503031042

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updated 1 day ago by JJ202503031042

3 replies • 197 views
Discussion

Recovering "actionable" netlist from GDS II

Category: Custom IC Design

By GS202507021424

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started 1 day ago

0 replies • 45 views
Discussion

Creating Assura DRC rule to check that sep of 2 layers is exactly 2 different values

Category: Custom IC Design

By Miguel V

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started 2 days ago

0 replies • 63 views
Discussion

LVS Warning: “Unattached port label” for PLUS/MINUS on layer ind11_text — can’t locate device

Category: Custom IC Design

By RK202509013321

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updated 2 days ago by RobMan

3 replies • 311 views
Discussion

PSS + PSTB for Buck converter

Category: Custom IC Design

By TH202510293247

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updated 2 days ago by Frank Wiedmann

11 replies • 551 views
Discussion

Dual Core Oscillator Open Loop

Category: Custom IC Design

By IS20250922772

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started 2 days ago

0 replies • 72 views
Discussion

Assembler: possible to disable automatic evaluation of output expressions?

Category: Custom IC Design

By dontpanic

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updated 2 days ago by Andrew Beckett

1 replies • 161 views
Discussion

Assembler: possible to force inclusion of model file(s) at the very beginning of netlist?

Category: Custom IC Design

By dontpanic

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updated 2 days ago by Andrew Beckett

3 replies • 360 views

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