Custom IC Design

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Discussion

how to generate spectre netlist for all the schematics in 1 lib ?

Category: Custom IC Design

By Nhumai

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updated over 6 years ago by Andrew Beckett

11 replies • 19688 views
Discussion

Encounter

Category: Custom IC Design

By Pinjare

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updated over 6 years ago by Andrew Beckett

2 replies • 14177 views
Discussion

output log shows sim finish, but assembler result still runing

Category: Custom IC Design

By sjwprc

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updated over 6 years ago by Andrew Beckett

3 replies • 16324 views
Discussion

Current state of the IC Design industry in the US

Category: Custom IC Design

By charm16

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started over 6 years ago

0 replies • 13508 views
Discussion

Matlab filtered PRBS inport in Cadence.

Category: Custom IC Design

By AllenD

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updated over 6 years ago by Frank Wiedmann

3 replies • 15330 views
Discussion

ERROR (SPECTRE-16080): No DC solution found (no convergence).

Category: Custom IC Design

By vinod joshi

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updated over 6 years ago by RiadKaced

1 replies • 18554 views
Discussion

IC5141 core dump when launching icfb

Category: Custom IC Design

By rflayout

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updated over 6 years ago by RiadKaced

2 replies • 14914 views
Discussion

How to change the m factor (multiplication factor) for Instances in cadence

Category: Custom IC Design

By NorNand

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updated over 6 years ago by NorNand

2 replies • 16706 views
Discussion

netlist error for a particular resistor model

Category: Custom IC Design

By kadam

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updated over 6 years ago by RiadKaced

1 replies • 15717 views
Discussion

Bit pattern generator for mixed signal simulation

Category: Custom IC Design

By NorNand

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updated over 6 years ago by NorNand

4 replies • 19405 views
Discussion

Saving and plotting signal within DSPF using ade excell

Category: Custom IC Design

By eyalg

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updated over 6 years ago by RiadKaced

3 replies • 15373 views
Discussion

ERROR ADE-3036 in momSim

Category: Custom IC Design

By knark

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updated over 6 years ago by Andrew Beckett

1 replies • 14378 views
Discussion

SAVING net VOLTAGE and pin CURRENTS at block level and also saving current in the mos transistors pins in EXTRACTED view

Category: Custom IC Design

By Pyroblast

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updated over 6 years ago by RiadKaced

5 replies • 24560 views
Discussion

ADEXL:priority of jobs/runs

Category: Custom IC Design

By cato

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updated over 6 years ago by cato

2 replies • 2028 views
Discussion

Regarding Simulation time in nc-verilog and in ADE-L/XL + AMS

Category: Custom IC Design

By RFStuff

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updated over 6 years ago by RiadKaced

2 replies • 1412 views

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