Custom IC Design

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Discussion

LVS with Calibre ("wrong floating n-well" error)

Category: Custom IC Design

By Ueue

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updated over 13 years ago by Andrew Beckett

1 replies • 4332 views
Discussion

cross probing with calibre

Category: Custom IC Design

By layout analog

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updated over 13 years ago by Andrew Beckett

1 replies • 13114 views
Discussion

Location of spectre for ADE L

Category: Custom IC Design

By jun1119

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updated over 13 years ago by Andrew Beckett

1 replies • 12986 views
Discussion

VerilogIn pin notation

Category: Custom IC Design

By TjaartOpperman

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updated over 13 years ago by Andrew Beckett

1 replies • 13967 views
Discussion

Measure across a component in cadence ic 6.1.3

Category: Custom IC Design

By jun1119

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updated over 13 years ago by Andrew Beckett

1 replies • 13208 views
Discussion

Assura TIE ivpcell substrateLib not found

Category: Custom IC Design

By Xiongliang

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updated over 13 years ago by Andrew Beckett

1 replies • 13136 views
Discussion

Trendline like Excel

Category: Custom IC Design

By FormerMember

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updated over 13 years ago by Andrew Beckett

1 replies • 4557 views
Discussion

In valid dev or Device Instance in dc analysis of spectre cadence

Category: Custom IC Design

By leonel1408

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updated over 13 years ago by Andrew Beckett

1 replies • 13109 views
Discussion

Is it possible to run DRC in Virtuoso on command line

Category: Custom IC Design

By sanil

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updated over 13 years ago by Andrew Beckett

1 replies • 13574 views
Discussion

dcmatch appNote

Category: Custom IC Design

By mate0409

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updated over 13 years ago by FormerMember

5 replies • 14991 views
Discussion

Error: "Vim: Warning: Output is not to a terminal" when trying to open veriloga view

Category: Custom IC Design

By archive

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updated over 13 years ago by skillUser

2 replies • 3728 views
Discussion

command to return the TechLib of the current design window (layout editor window)

Category: Custom IC Design

By jaleco

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updated over 13 years ago by jaleco

3 replies • 13704 views
Discussion

Converting mosaic of syContacts devices from IC5 to IC6 ( cdb2oa )

Category: Custom IC Design

By bnugent

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updated over 13 years ago by bnugent

2 replies • 13272 views
Discussion

Assura41 ELW, VLW resize: CPU load 101%

Category: Custom IC Design

By LayMan

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updated over 13 years ago by LayMan

2 replies • 13469 views
Discussion

Exporting DC operating point

Category: Custom IC Design

By mailavj

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updated over 13 years ago by Andrew Beckett

1 replies • 13542 views

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