Custom IC Design

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Discussion

Unit of self_gain in BSIM4(V4.5)

Category: Custom IC Design

By wgtkan

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updated over 5 years ago by Andrew Beckett

8 replies • 3247 views
Discussion

Exporting Cell Count and Cell Layers to text file

Category: Custom IC Design

By FLNaviGator

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started over 5 years ago

0 replies • 12487 views
Discussion

liberate error messages doc.

Category: Custom IC Design

By chaujohnthan

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updated over 5 years ago by Andrew Beckett

1 replies • 13282 views
Discussion

Noise analysis on dynamic comparator

Category: Custom IC Design

By minci

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updated over 5 years ago by Andrew Beckett

15 replies • 28224 views
Discussion

Noise spectral density of an amplifier

Category: Custom IC Design

By subhajitdey20

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updated over 5 years ago by Andrew Beckett

3 replies • 14538 views
Discussion

fsdb file not refreshed during simulation

Category: Custom IC Design

By Karev11

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updated over 5 years ago by Andrew Beckett

2 replies • 16118 views
Discussion

ADE L plotting error: vector::_M_range_check

Category: Custom IC Design

By ZoltanT

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updated over 5 years ago by Andrew Beckett

1 replies • 1466 views
Discussion

Some DRC errors regarding SP and DP

Category: Custom IC Design

By annieglez92

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updated over 5 years ago by annieglez92

2 replies • 13983 views
Discussion

Conversion of old Simulation Files

Category: Custom IC Design

By JavadBa

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updated over 5 years ago by JavadBa

4 replies • 13882 views
Discussion

plotting waveVsWave across corner+global variable sweep in ADEXL

Category: Custom IC Design

By dzakharian

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started over 5 years ago

0 replies • 1416 views
Discussion

double tail comparator input refered offset voltage measured using cadence

Category: Custom IC Design

By nkataria

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updated over 5 years ago by sypetre

8 replies • 18388 views
Discussion

Spectre S-parameter analysis

Category: Custom IC Design

By cADEUser

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updated over 5 years ago by Andrew Beckett

12 replies • 36689 views
Discussion

How do I load parametric analysis results in ADE L again to plot

Category: Custom IC Design

By Nader Fathy

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updated over 5 years ago by Nader Fathy

4 replies • 18029 views
Discussion

Export Netlist with VerilogA subblock when there is no ADE license

Category: Custom IC Design

By quyleanh

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updated over 5 years ago by quyleanh

8 replies • 16359 views
Discussion

fsdb to pwl

Category: Custom IC Design

By KOTB

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updated over 5 years ago by Andrew Beckett

4 replies • 18101 views

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