Custom IC Design

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Discussion

Unable to place pins to level-1 pins

Category: Custom IC Design

By RuihW
•
updated over 1 year ago by RuihW

1 replies • 4566 views
Discussion

Adjusting circuit parameters led to the failure of Spectre simulation

Category: Custom IC Design

By liangqunshan
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updated over 1 year ago by Andrew Beckett

1 replies • 4074 views
Discussion

Complex Port Value for transient results

Category: Custom IC Design

By EngrZM
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updated over 1 year ago by Frank Wiedmann

6 replies • 5964 views
Discussion

Toolbars items

Category: Custom IC Design

By RicardoGV1
•
updated over 1 year ago by RicardoGV1

2 replies • 4354 views
Discussion

Pass-gate pmos during vdd rise - forward bias diode (b-d/s)

Category: Custom IC Design

By IKIF
•
started over 1 year ago

0 replies • 449 views
Discussion

How to use calculator functions like value(), cross(), or abCrossTwoWaves() for array-like signals?

Category: Custom IC Design

By DomiHammerfall
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started over 1 year ago

0 replies • 5137 views
Discussion

spectre: save parameter before alter statement and revert for later analyses

Category: Custom IC Design

By Zol
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started over 1 year ago

0 replies • 4079 views
Discussion

Temperature in ocean script

Category: Custom IC Design

By Martinsh
•
updated over 1 year ago by Martinsh

2 replies • 4453 views
Discussion

Cadence License Error (DB-320001)

Category: Custom IC Design

By Leo 93
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updated over 1 year ago by Andrew Beckett

4 replies • 5849 views
Discussion

ADEXL 1921 failed to start problem with virtuoso IC6.18

Category: Custom IC Design

By hesaliveJim
•
updated over 1 year ago by Andrew Beckett

3 replies • 5415 views
Discussion

With large Verilog-A, SPECTRE fails to run

Category: Custom IC Design

By mfkasim1
•
started over 1 year ago

0 replies • 4050 views
Discussion

Very slow ADEXL datasheet generation

Category: Custom IC Design

By markris
•
updated over 1 year ago by markris

7 replies • 5733 views
Discussion

Liberate license issue

Category: Custom IC Design

By VardhanPES
•
updated over 1 year ago by Guangjun Cao

1 replies • 7042 views
Discussion

Verilog-A syntax error with user-defined function and if-else statement

Category: Custom IC Design

By gjeong35
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updated over 1 year ago by Andrew Beckett

1 replies • 6034 views
Discussion

How to short two nets with different names in layout.

Category: Custom IC Design

By mars32
•
updated over 1 year ago by Andrew Beckett

1 replies • 5232 views

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