Custom IC Design

Latest Posts

Discussion

Maestro customization: Not to open schematic in tab, and two other issues

Category: Custom IC Design

By HoWei

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 14993 views
Discussion

Maestro: Could not find state ..../spectre/active active

Category: Custom IC Design

By HoWei

$usertype
•
updated over 6 years ago by HoWei

9 replies • 5984 views
Discussion

VerilogA, one or the other parameter implementation

Category: Custom IC Design

By Emiel

$usertype
•
updated over 6 years ago by Emiel

4 replies • 14017 views
Discussion

"readns" cannot read state-file in DC Corner Simulation

Category: Custom IC Design

By Chenbt

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 1271 views
Discussion

Simulation with dspf_include

Category: Custom IC Design

By BrJaWr

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 14629 views
Discussion

Adding dummy elements to the layout

Category: Custom IC Design

By NorNand

$usertype
•
updated over 6 years ago by NorNand

4 replies • 18446 views
Discussion

Sprctre simulation with no schematic cells....

Category: Custom IC Design

By AllenD

$usertype
•
updated over 6 years ago by Andrew Beckett

1 replies • 13066 views
Discussion

Changing default editor within ADE

Category: Custom IC Design

By BrJaWr

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 14134 views
Discussion

PSS simulation

Category: Custom IC Design

By svilen

$usertype
•
updated over 6 years ago by JackieTheBanan

13 replies • 28189 views
Discussion

Model of Transient Noise Simulation in Cadence

Category: Custom IC Design

By Zhao Hui

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 13787 views
Discussion

Is there any tips & simulator settings to accelerate tran initial converge of ams top analog&digital simulation ?

Category: Custom IC Design

By Zest

$usertype
•
updated over 6 years ago by Andrew Beckett

2 replies • 1081 views
Discussion

Save subcircuit instance nets in ADE Assembler

Category: Custom IC Design

By NZimmermann

$usertype
•
updated over 6 years ago by NZimmermann

2 replies • 15636 views
Discussion

Abstract LEF files with Abstract generator

Category: Custom IC Design

By fengye

$usertype
•
updated over 6 years ago by fengye

2 replies • 15618 views
Discussion

"Assura has not been installed in this hierarchy" Error

Category: Custom IC Design

By nokta

$usertype
•
updated over 6 years ago by nokta

2 replies • 3598 views
Discussion

use output signals from other circuits as input for simulation

Category: Custom IC Design

By BaaB

$usertype
•
updated over 6 years ago by Andrew Beckett

3 replies • 15714 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.