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Custom IC Design

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  • Discussion

    Layout XL stop layers (again)

    Category: Custom IC Design

    By tdtg

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    updated over 2 years ago by tdtg

    2 replies • 8720 views
  • Discussion

    Availability of Sensitivity results in Assembler after corner run?

    Category: Custom IC Design

    By StephanWeber

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    updated over 2 years ago by Andrew Beckett

    1 replies • 7377 views
  • Discussion

    How to re-use a setting for Assembler Results Table (Detailed Transposed)?

    Category: Custom IC Design

    By StephanWeber

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    updated over 2 years ago by Andrew Beckett

    1 replies • 7005 views
  • Discussion

    unwrap family

    Category: Custom IC Design

    By Brad RFeng

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    updated over 2 years ago by Andrew Beckett

    1 replies • 7194 views
  • Discussion

    Virtuoso command not found

    Category: Custom IC Design

    By VoTuanMinh

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    updated over 2 years ago by Andrew Beckett

    21 replies • 25074 views
  • Discussion

    How to use corner output expression in other corners for a multiple corner sim?

    Category: Custom IC Design

    By vpeddireddy

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    updated over 2 years ago by Andrew Beckett

    4 replies • 10165 views
  • Discussion

    Liberate: are only hidden power arcs needed when defining power arcs during STD cell characterisation?

    Category: Custom IC Design

    By jiacong

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    started over 2 years ago

    0 replies • 7085 views
  • Discussion

    Schematic bus terminals has no corresponding layout bus terminal definition

    Category: Custom IC Design

    By sidm

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    updated over 2 years ago by sidm

    3 replies • 8290 views
  • Discussion

    Bus termination error?

    Category: Custom IC Design

    By kenc184

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    updated over 2 years ago by Andrew Beckett

    8 replies • 10402 views
  • Discussion

    How can I quickly check the run date of a History item in Assembler from Data View assistant?

    Category: Custom IC Design

    By StephanWeber

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    updated over 2 years ago by Andrew Beckett

    4 replies • 8074 views
  • Discussion

    iv characteristics of solar cell in cadence virtuoso

    Category: Custom IC Design

    By isiaka099

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    started over 2 years ago

    0 replies • 6630 views
  • Discussion

    Binding issue with digitally synthesized block

    Category: Custom IC Design

    By sidm

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    started over 2 years ago

    0 replies • 6710 views
  • Discussion

    Layout Editor: Pin Visibility for Sub-Levels

    Category: Custom IC Design

    By sgcad

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    •

    updated over 2 years ago by Andrew Beckett

    3 replies • 10090 views
  • Discussion

    1/f corner calculation for noise analyses

    Category: Custom IC Design

    By illaoi

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    updated over 2 years ago by Andrew Beckett

    1 replies • 2421 views
  • Discussion

    spectrumMeasurement function

    Category: Custom IC Design

    By sidm

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    •

    updated over 2 years ago by ShawnLogan

    5 replies • 9712 views
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