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Custom IC Design

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  • Discussion

    Problems with expressions in Monte Carlo

    Category: Custom IC Design

    By Karo Karo

    •

    updated over 15 years ago by Karo

    6 replies • 14491 views
  • Discussion

    Check in Spectre license automatically

    Category: Custom IC Design

    By archive archive

    •

    updated over 15 years ago by archive

    2 replies • 15145 views
  • Discussion

    how to run the simulaiton for 1 ns step interval ..?

    Category: Custom IC Design

    By Sunil Kumar K Sunil Kumar K

    •

    updated over 15 years ago by Sunil Kumar K

    5 replies • 14122 views
  • Discussion

    Text output on Cadence Composer

    Category: Custom IC Design

    By archive archive

    •

    updated over 15 years ago by Andrew Beckett

    4 replies • 13383 views
  • Discussion

    creating a matrix of instances in verilog-A

    Category: Custom IC Design

    By rickrevolta rickrevolta

    •

    updated over 15 years ago by Andrew Beckett

    2 replies • 16263 views
  • Discussion

    Pin names

    Category: Custom IC Design

    By StreamCX StreamCX

    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 10193 views
  • Discussion

    LvsIgnore Properties

    Category: Custom IC Design

    By frogconsultant frogconsultant

    •

    updated over 15 years ago by frogconsultant

    12 replies • 30134 views
  • Discussion

    How to implement this equation in VerilogA

    Category: Custom IC Design

    By princemahmmod princemahmmod

    •

    updated over 15 years ago by Andrew Beckett

    4 replies • 15539 views
  • Discussion

    Cadence 6 waveform error vpwl vsrc

    Category: Custom IC Design

    By StreamCX StreamCX

    •

    updated over 15 years ago by StreamCX

    9 replies • 8959 views
  • Discussion

    Output SPEF-file from QRC contains only top level ports

    Category: Custom IC Design

    By Slawa Slawa

    •

    updated over 15 years ago by Quek

    1 replies • 6075 views
  • Discussion

    Off-Grid pins warning in abstract generation

    Category: Custom IC Design

    By affaq affaq

    •

    updated over 15 years ago by Alex Soyer

    3 replies • 13711 views
  • Discussion

    subciruit initiated top-level current probe

    Category: Custom IC Design

    By Kalimero Kalimero

    •

    updated over 15 years ago by Kalimero

    5 replies • 16134 views
  • Discussion

    cadence verilog ams environment setup question

    Category: Custom IC Design

    By Wing2 Wing2

    •

    updated over 15 years ago by EricCDN

    1 replies • 18055 views
  • Discussion

    How to short small resistor for lvs purpose

    Category: Custom IC Design

    By harleyMax harleyMax

    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 19007 views
  • Discussion

    Manual editing of a p2lvsfile

    Category: Custom IC Design

    By Slawa Slawa

    •

    updated over 15 years ago by Slawa

    6 replies • 7411 views
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