Custom IC Design

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Discussion

ddt() at a certain timestep in Verilog-A

Category: Custom IC Design

By rhanna

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updated over 4 years ago by Andrew Beckett

11 replies • 17955 views
Discussion

Layout XL generating MOS without source contacts.

Category: Custom IC Design

By hesaliveJim

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updated over 4 years ago by henker

2 replies • 12863 views
Discussion

Is there a way to exclude vias when highlighting nets using Net Tracer on Virtuoso?

Category: Custom IC Design

By Tom Sawyer

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started over 4 years ago

0 replies • 10912 views
Discussion

can analog pad be used as power pad (power is ac sinosuid)

Category: Custom IC Design

By Her1

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updated over 4 years ago by Her1

6 replies • 13206 views
Discussion

HB Analysis on PLL

Category: Custom IC Design

By fortune100worse

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updated over 4 years ago by Andrew Beckett

20 replies • 27700 views
Discussion

How to update schematic without layout

Category: Custom IC Design

By AlexST

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updated over 4 years ago by Andrew Beckett

1 replies • 11109 views
Discussion

ADE XL simluation stuck

Category: Custom IC Design

By Holz

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updated over 4 years ago by FormerMember

5 replies • 16722 views
Discussion

Virtuoso Spice In Device Map property is not honored

Category: Custom IC Design

By Nader Fathy

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updated over 4 years ago by Nader Fathy

6 replies • 22039 views
Discussion

Layout offgrid problem

Category: Custom IC Design

By Senan

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updated over 4 years ago by Senan

4 replies • 18756 views
Discussion

Naming a net with repetitively with same net name in schematic?

Category: Custom IC Design

By nvyayla

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updated over 4 years ago by JaydeepDalwadi

3 replies • 19078 views
Discussion

Automated way for creating custom layout cell view for polygon shapes

Category: Custom IC Design

By sidm

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updated over 4 years ago by sidm

4 replies • 12322 views
Discussion

Spectre terminated due to fatal error

Category: Custom IC Design

By SSRRaayy

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updated over 4 years ago by Andrew Beckett

1 replies • 13351 views
Discussion

some questions after using abConvertComponentParams.il to do schematic porting

Category: Custom IC Design

By ringamp

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updated over 4 years ago by Andrew Beckett

5 replies • 13237 views
Discussion

Cannot plot transient response (no graph/empty window)

Category: Custom IC Design

By hikotoshi

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updated over 4 years ago by yysunj

22 replies • 16252 views
Discussion

DRC DIVA. How can I solve this marker text: "Space to three adjacent Contacts ( < 0.10um apart) >= 0.08 um"?

Category: Custom IC Design

By VictorArzate

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updated over 4 years ago by Andrew Beckett

3 replies • 2487 views

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