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Custom IC Design

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  • Discussion

    How to do a sp simulation using the netlist created by relxpert?

    Category: Custom IC Design

    By wyliechee

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    updated over 13 years ago by Andrew Beckett

    3 replies • 13982 views
  • Discussion

    Cadence session crash.

    Category: Custom IC Design

    By maskdesigner

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    •

    updated over 13 years ago by Andrew Beckett

    5 replies • 16918 views
  • Discussion

    LVS with Calibre ("wrong floating n-well" error)

    Category: Custom IC Design

    By Ueue

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 4683 views
  • Discussion

    cross probing with calibre

    Category: Custom IC Design

    By layout analog

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13864 views
  • Discussion

    Location of spectre for ADE L

    Category: Custom IC Design

    By jun1119

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13719 views
  • Discussion

    VerilogIn pin notation

    Category: Custom IC Design

    By TjaartOpperman

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 14817 views
  • Discussion

    Measure across a component in cadence ic 6.1.3

    Category: Custom IC Design

    By jun1119

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13927 views
  • Discussion

    Assura TIE ivpcell substrateLib not found

    Category: Custom IC Design

    By Xiongliang

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13845 views
  • Discussion

    Trendline like Excel

    Category: Custom IC Design

    By FormerMember

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 4696 views
  • Discussion

    In valid dev or Device Instance in dc analysis of spectre cadence

    Category: Custom IC Design

    By leonel1408

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    •

    updated over 13 years ago by Andrew Beckett

    1 replies • 13835 views
  • Discussion

    Is it possible to run DRC in Virtuoso on command line

    Category: Custom IC Design

    By sanil

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    updated over 13 years ago by Andrew Beckett

    1 replies • 14352 views
  • Discussion

    dcmatch appNote

    Category: Custom IC Design

    By mate0409

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    •

    updated over 13 years ago by FormerMember

    5 replies • 15927 views
  • Discussion

    Error: "Vim: Warning: Output is not to a terminal" when trying to open veriloga view

    Category: Custom IC Design

    By archive

    $usertype

    •

    updated over 13 years ago by skillUser

    2 replies • 4047 views
  • Discussion

    command to return the TechLib of the current design window (layout editor window)

    Category: Custom IC Design

    By jaleco

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    •

    updated over 13 years ago by jaleco

    3 replies • 14500 views
  • Discussion

    Converting mosaic of syContacts devices from IC5 to IC6 ( cdb2oa )

    Category: Custom IC Design

    By bnugent

    $usertype

    •

    updated over 13 years ago by bnugent

    2 replies • 14059 views
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