Custom IC Design

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mtline physical length

Category: Custom IC Design

By Karev11

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updated over 9 years ago by Andrew Beckett

1 replies • 16969 views
Discussion

SPECTRE-18023: Parasitics RC reduction disabled (fast APS)

Category: Custom IC Design

By vivkr

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updated over 9 years ago by vivkr

3 replies • 16740 views
Discussion

Failing to plot expressions that include variables in ADE (G)XL

Category: Custom IC Design

By LuisGutierrez

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updated over 9 years ago by Andrew Beckett

1 replies • 788 views
Discussion

Verilog - AMS model for powerFET

Category: Custom IC Design

By Divy

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updated over 9 years ago by Andrew Beckett

10 replies • 3025 views
Discussion

DRC and LVS body floating problem

Category: Custom IC Design

By Manp

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updated over 9 years ago by Andrew Beckett

1 replies • 16405 views
Discussion

Get help about a parameter using command

Category: Custom IC Design

By BaaB

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updated over 9 years ago by BaaB

4 replies • 15518 views
Discussion

Scaling Factors

Category: Custom IC Design

By BaaB

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started over 9 years ago

0 replies • 15483 views
Discussion

Virtuoso ADE L calculator - delay function - Variable value in threshold field

Category: Custom IC Design

By Manp

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updated over 9 years ago by Manp

2 replies • 4395 views
Discussion

Easy way to connect a input bus pins in schematic

Category: Custom IC Design

By Johanny Saenz

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updated over 9 years ago by Andrew Beckett

2 replies • 18749 views
Discussion

Source file for ELDO simulation

Category: Custom IC Design

By UUinfini

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updated over 9 years ago by Andrew Beckett

1 replies • 14797 views
Discussion

Transient simulation accuracy

Category: Custom IC Design

By ymn2009

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updated over 9 years ago by Andrew Beckett

3 replies • 17575 views
Discussion

Verilog -A amp

Category: Custom IC Design

By black tea

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updated over 9 years ago by Andrew Beckett

5 replies • 10264 views
Discussion

Problem seeing the layout content of the instances

Category: Custom IC Design

By Neo2012

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updated over 9 years ago by Andrew Beckett

3 replies • 14614 views
Discussion

capgen error

Category: Custom IC Design

By Jaganath

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updated over 9 years ago by Andrew Beckett

1 replies • 13912 views
Discussion

If-else statement in VerilogA- Designing a memory element

Category: Custom IC Design

By Nishtha Sharma

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updated over 9 years ago by Nishtha Sharma

3 replies • 2833 views

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