Custom IC Design

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Discussion

How do I turn off flighlines from the bulk of transistors....

Category: Custom IC Design

By pham777

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updated over 11 years ago by Andrew Beckett

1 replies • 12916 views
Discussion

Component Display parameter missing in EDIT menu Cadence 6.1.6-64b

Category: Custom IC Design

By sasuke

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updated over 11 years ago by Marc Heise

1 replies • 15483 views
Discussion

Pins, Nets created are not visible

Category: Custom IC Design

By Prash123

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updated over 11 years ago by Andrew Beckett

1 replies • 13580 views
Discussion

Timestamp.....

Category: Custom IC Design

By pham777

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updated over 11 years ago by aflex

2 replies • 13126 views
Discussion

Reading a data file in Veriloga code

Category: Custom IC Design

By Sali

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updated over 11 years ago by Sali

4 replies • 17094 views
Discussion

help on using diode model in Spectre simulation

Category: Custom IC Design

By apple419

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updated over 11 years ago by Andrew Beckett

2 replies • 17149 views
Discussion

saving verilog-a triggers compilation instead of just syntax check

Category: Custom IC Design

By danmc

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updated over 11 years ago by danmc

2 replies • 13286 views
Discussion

sweep variable "bs" in hb, then use VAR("bs") in output expression, not plot in ADEXL

Category: Custom IC Design

By Taoni

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updated over 11 years ago by Andrew Beckett

6 replies • 7036 views
Discussion

Strange behavior of traponly method (MMSIM/SpectreRF)

Category: Custom IC Design

By norrin

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updated over 11 years ago by Frank Wiedmann

2 replies • 11304 views
Discussion

issue with (* cds_inherited_parameter *)

Category: Custom IC Design

By Fabb

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updated over 11 years ago by Fabb

4 replies • 14478 views
Discussion

How to use calculator to process a set of curves in wavescan

Category: Custom IC Design

By bjstroll

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updated over 11 years ago by Andrew Beckett

1 replies • 15246 views
Discussion

Extraction AS/AD in Assura RCX

Category: Custom IC Design

By TiNat

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updated over 11 years ago by Andrew Beckett

1 replies • 684 views
Discussion

ocean -nograph error

Category: Custom IC Design

By nigam214

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updated over 11 years ago by Andrew Beckett

6 replies • 3501 views
Discussion

During pcell evaluation in Assura LVS, is there a way to get cellview database information ?

Category: Custom IC Design

By windowsdee

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updated over 11 years ago by Andrew Beckett

1 replies • 12940 views
Discussion

LVS on a layout imported from Encounter versus the Physical Verilog netlist

Category: Custom IC Design

By Kabal

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updated over 11 years ago by Andrew Beckett

14 replies • 23526 views

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