Custom IC Design

Latest Posts

Discussion

Changing font in "graph summary labels"

Category: Custom IC Design

By rrihak

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started over 2 years ago

0 replies • 706 views
Discussion

Save certain waveform after simulations end while preserving corner order

Category: Custom IC Design

By Zaara

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updated over 2 years ago by ShawnLogan

4 replies • 6975 views
Discussion

Setting default independent variable in ADE Explorer/Assembler

Category: Custom IC Design

By CSCNalu

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updated over 2 years ago by Andrew Beckett

1 replies • 1139 views
Discussion

adexl does not run neither multicorner nor montecarlo simulations

Category: Custom IC Design

By gnangotzi

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started over 2 years ago

0 replies • 5713 views
Discussion

Single layer auto-routing

Category: Custom IC Design

By sumbadee

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started over 2 years ago

0 replies • 5950 views
Discussion

Hierarchical Net Name Preservation in Quantus

Category: Custom IC Design

By Anas Wanas

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started over 2 years ago

0 replies • 6125 views
Discussion

multiple power pads when global supply name used in sub blocks?

Category: Custom IC Design

By kenc184

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updated over 2 years ago by kenc184

9 replies • 9366 views
Discussion

Plot Vdsat from DC sweep analysis?

Category: Custom IC Design

By StephanWeber

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updated over 2 years ago by Andrew Beckett

4 replies • 8307 views
Discussion

Impedance matching

Category: Custom IC Design

By Shanci Hu

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updated over 2 years ago by StephanWeber

1 replies • 6630 views
Discussion

problems with pspice model when simulating with spectre

Category: Custom IC Design

By liangqunshan

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updated over 2 years ago by liangqunshan

6 replies • 8264 views
Discussion

RUN PLAN : The 'analyses' section of the runplan test does not reflect the active setup.

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

5 replies • 2181 views
Discussion

RUN PLAN : Is there a way to know the total number of "point sweeps" in a given runplan similar to how the active setup shows in the run summary.

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

2 replies • 1101 views
Discussion

how to create a custom constraint group for Layout XL connectivity

Category: Custom IC Design

By sc07734

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updated over 2 years ago by RobMan

5 replies • 10018 views
Discussion

Is there a way to check edge to edge separation using Assura 4.16

Category: Custom IC Design

By Florent Jehannin

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updated over 2 years ago by Florent Jehannin

2 replies • 6149 views
Discussion

How to set different views for the same cell in different instances?

Category: Custom IC Design

By zuiying

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updated over 2 years ago by Andrew Beckett

1 replies • 7820 views

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