Custom IC Design

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Discussion

What's the difference between gate level extraction and transistor level extraction in Calibre xRC tool.

Category: Custom IC Design

By Biasing

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updated over 9 years ago by Biasing

2 replies • 12260 views
Discussion

How do you annotate region of operation for NMOS transistors in Cadence Virtuoso?

Category: Custom IC Design

By ocho

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updated over 9 years ago by Andrew Beckett

1 replies • 24303 views
Discussion

Assura LVS Error (Execution Terminated)

Category: Custom IC Design

By Sattar72

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updated over 9 years ago by Andrew Beckett

7 replies • 19640 views
Discussion

How to find the mobility of mos in 45nm technology library

Category: Custom IC Design

By vinod joshi

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updated over 9 years ago by Andrew Beckett

1 replies • 22440 views
Discussion

How to simulate initial condition for post-layout simulation?

Category: Custom IC Design

By BaaB

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updated over 9 years ago by Andrew Beckett

1 replies • 15280 views
Discussion

Problem in Monte Carlo with XPS MS

Category: Custom IC Design

By rsashwinkumar

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updated over 9 years ago by Andrew Beckett

1 replies • 15064 views
Discussion

Simulate all possible value of a MOSFET threshold voltage

Category: Custom IC Design

By BaaB

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updated over 9 years ago by BaaB

4 replies • 15658 views
Discussion

How to parameterize a string parameter in ADE XL?

Category: Custom IC Design

By rickyuexu

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started over 9 years ago

0 replies • 14352 views
Discussion

Assura QRC Error

Category: Custom IC Design

By sdineshkumar

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updated over 9 years ago by Andrew Beckett

3 replies • 16992 views
Discussion

select master cell in ADEXL

Category: Custom IC Design

By Clidre

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updated over 9 years ago by Andrew Beckett

1 replies • 13750 views
Discussion

Extracting Interconnect Parameters

Category: Custom IC Design

By rafaelon

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updated over 9 years ago by rafaelon

2 replies • 14163 views
Discussion

Error during the RC extraction using 45 nm technology

Category: Custom IC Design

By vinod joshi

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updated over 9 years ago by Andrew Beckett

1 replies • 14093 views
Discussion

lineread command error out when trying to read a verilog generation log file

Category: Custom IC Design

By mlea

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updated over 9 years ago by Andrew Beckett

1 replies • 14236 views
Discussion

Pass Path and Filename via Variable in ADEXL

Category: Custom IC Design

By SebastianS

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started over 9 years ago

0 replies • 15502 views
Discussion

"FATAL: Insufficient memory available" spectre issue

Category: Custom IC Design

By Dresdener

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updated over 9 years ago by Dresdener

2 replies • 6854 views

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