Custom IC Design

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Discussion

Spectre parallel jobs reduce near finish

Category: Custom IC Design

By Pirate King

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updated over 2 years ago by Cadenceuser101

6 replies • 9249 views
Discussion

Simulating a circuit in an array

Category: Custom IC Design

By delgsy

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updated over 2 years ago by Andrew Beckett

3 replies • 7072 views
Discussion

Virtuoso SystemVerilog errors

Category: Custom IC Design

By HoWei

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updated over 2 years ago by HoWei

14 replies • 14749 views
Discussion

Multiple alignment spacing parameters

Category: Custom IC Design

By Kevin Buck

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updated over 2 years ago by Kevin Buck

2 replies • 7172 views
Discussion

STB Analysis: Invalid instance name

Category: Custom IC Design

By fyoh

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updated over 2 years ago by fyoh

6 replies • 9562 views
Discussion

ADE Results "Detailed - Transposed" and CSV export: Missing spec and testname

Category: Custom IC Design

By StephanWeber

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updated over 2 years ago by StephanWeber

3 replies • 1634 views
Discussion

Magnitude value in AC simulation with Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 2 years ago by ShawnLogan

11 replies • 19295 views
Discussion

Convolution function of two temporal signals in Cadence Verilog-A

Category: Custom IC Design

By cheedyliew

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started over 2 years ago

0 replies • 6448 views
Discussion

Design and placement of hard macros

Category: Custom IC Design

By toufiqhanik

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started over 2 years ago

0 replies • 6760 views
Discussion

Failed to open the GUI of Cadence Abstract Generator

Category: Custom IC Design

By Hongming Lyu

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updated over 2 years ago by Alex Soyer

2 replies • 6914 views
Discussion

Which instance model parameters does Spectre save?

Category: Custom IC Design

By Brad RFeng

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updated over 2 years ago by Andrew Beckett

7 replies • 8584 views
Discussion

Running OCEAN XL sweep with a netlist instead of a lib/cel/view

Category: Custom IC Design

By AncisMichele

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updated over 2 years ago by Andrew Beckett

8 replies • 3037 views
Discussion

Behavioral modelling using verilogA for a TIA

Category: Custom IC Design

By TUKA

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updated over 2 years ago by TUKA

3 replies • 7549 views
Discussion

Layout output pins changing the behaviour of extracted netlist

Category: Custom IC Design

By Andres S

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started over 2 years ago

0 replies • 6580 views
Discussion

Adexl - interactive history does not display design variables

Category: Custom IC Design

By firebolt

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updated over 2 years ago by firebolt

2 replies • 1235 views

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