Custom IC Design

Latest Posts

Discussion

Control position of instance placement in an ihdl imported schematic

Category: Custom IC Design

By mrharris
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updated 6 months ago by Andrew Beckett

1 replies • 1638 views
Discussion

Finding EAD/ICT file for running parasitic Extraction in Virtuoso EXL

Category: Custom IC Design

By AL202502074331
•
updated 6 months ago by Andrew Beckett

1 replies • 540 views
Discussion

Y-axis units and labels when plotting from ADE

Category: Custom IC Design

By mikewu999
•
updated 6 months ago by Andrew Beckett

2 replies • 1851 views
Discussion

Back and forward history buttons in Schematic Editor clearing probed nets?

Category: Custom IC Design

By ES20241003727
•
updated 6 months ago by Andrew Beckett

2 replies • 1742 views
Discussion

Enabling disk-space-check via .cdsinit

Category: Custom IC Design

By HoWei
•
started 7 months ago

0 replies • 1478 views
Discussion

Installscape issue on Rocky linux8/9 and Almalinux 9

Category: Custom IC Design

By CB202409064221
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updated 7 months ago by CB202409064221

3 replies • 1293 views
Discussion

Virtuoso Schematic shows graphically different values than query

Category: Custom IC Design

By WRM
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updated 7 months ago by WRM

2 replies • 1884 views
Discussion

Unable to remove text labels after flattening layout pcell

Category: Custom IC Design

By Ma100B
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updated 7 months ago by Ma100B

5 replies • 2384 views
Discussion

Maestro - problem with sweeping a transistor parameter because of netlist format

Category: Custom IC Design

By frankp
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updated 7 months ago by frankp

2 replies • 668 views
Discussion

Skill function to set x- or y-axis to linear scale

Category: Custom IC Design

By TB202408221839
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started 7 months ago

0 replies • 338 views
Discussion

Merge buses when creating a symbol from SpectreText netlist

Category: Custom IC Design

By ArthurP
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started 7 months ago

0 replies • 1572 views
Discussion

Can move component only up/down or left/right in Cadence Virtuoso

Category: Custom IC Design

By NN202501183253
•
updated 7 months ago by RobMan

1 replies • 700 views
Discussion

analogLib/bsource component with complex coefficient

Category: Custom IC Design

By TommasoF
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updated 7 months ago by TommasoF

3 replies • 756 views
Discussion

Is it possible to access design variable as parameter of systemverilog bloc

Category: Custom IC Design

By Mathieu Chene
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started 7 months ago

0 replies • 1584 views
Discussion

Issue OSSPDA with xcellium AMS sim

Category: Custom IC Design

By Binhngo1210
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started 7 months ago

0 replies • 1584 views

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