Custom IC Design

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Discussion

Creating a user defined Voltage source

Category: Custom IC Design

By Debajit B
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updated over 11 years ago by Debajit B

3 replies • 14592 views
Discussion

ocnxlRun never returns as some splits are hung forever

Category: Custom IC Design

By Tajinder
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updated over 11 years ago by Tajinder

3 replies • 13294 views
Discussion

SpiceIn - how to map to a total width from w and m in the CDL

Category: Custom IC Design

By WMACH
•
updated over 11 years ago by skillUser

4 replies • 4588 views
Discussion

" *Error* plus: can't handle (nil + nil) " during netlisting in icfb

Category: Custom IC Design

By yayla
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updated over 11 years ago by shila sh

7 replies • 14383 views
Discussion

AMS simulation taking very small step sizes. Help in finding offending connect modules?

Category: Custom IC Design

By Amblikai
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started over 11 years ago

0 replies • 13138 views
Discussion

Issue with DRC - "run is invalid"

Category: Custom IC Design

By apaj
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updated over 11 years ago by Quek

10 replies • 4430 views
Discussion

Extracting generic devices with Assura

Category: Custom IC Design

By PietroUser
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updated over 11 years ago by Andrew Beckett

3 replies • 13466 views
Discussion

Abstract Generator : abstract view with just "M1 net layer" => instead of "M1 drawing" and "M1 pin layers"

Category: Custom IC Design

By samung
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updated over 11 years ago by samung

2 replies • 1649 views
Discussion

Assura Layout extract.rul debug

Category: Custom IC Design

By PietroUser
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updated over 11 years ago by PietroUser

2 replies • 13099 views
Discussion

Is there a function in verilogA like "break" in C or C++ ?

Category: Custom IC Design

By UUinfini
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updated over 11 years ago by Andrew Beckett

1 replies • 1502 views
Discussion

Abstract Generator : tech file and origin in LEF file

Category: Custom IC Design

By samung
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updated over 11 years ago by samung

2 replies • 15737 views
Discussion

Pin definition in layout.oa (layer, connectivity) ?

Category: Custom IC Design

By samung
•
updated over 11 years ago by samung

2 replies • 15920 views
Discussion

Delay calculation for full adder circuit

Category: Custom IC Design

By KISHORE085
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updated over 11 years ago by KISHORE085

7 replies • 18344 views
Discussion

Virtuoso Editor Tools Menu

Category: Custom IC Design

By Octavian
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updated over 11 years ago by Octavian

2 replies • 13515 views
Discussion

Parametric analysis - voltage error in the netlist

Category: Custom IC Design

By Seokhyun Jeong
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updated over 11 years ago by Seokhyun Jeong

2 replies • 904 views

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