Custom IC Design

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Assura QRC Error

Category: Custom IC Design

By sdineshkumar

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updated over 9 years ago by Andrew Beckett

3 replies • 16234 views
Discussion

select master cell in ADEXL

Category: Custom IC Design

By Clidre

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updated over 9 years ago by Andrew Beckett

1 replies • 13179 views
Discussion

Extracting Interconnect Parameters

Category: Custom IC Design

By rafaelon

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updated over 9 years ago by rafaelon

2 replies • 13573 views
Discussion

Error during the RC extraction using 45 nm technology

Category: Custom IC Design

By vinod joshi

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updated over 9 years ago by Andrew Beckett

1 replies • 13508 views
Discussion

lineread command error out when trying to read a verilog generation log file

Category: Custom IC Design

By mlea

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updated over 9 years ago by Andrew Beckett

1 replies • 13619 views
Discussion

Pass Path and Filename via Variable in ADEXL

Category: Custom IC Design

By SebastianS

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started over 9 years ago

0 replies • 14908 views
Discussion

"FATAL: Insufficient memory available" spectre issue

Category: Custom IC Design

By Dresdener

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updated over 9 years ago by Dresdener

2 replies • 6439 views
Discussion

Help with Verilog-A file operation tasks

Category: Custom IC Design

By Reks

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updated over 9 years ago by Andrew Beckett

1 replies • 14507 views
Discussion

Sweep vth values

Category: Custom IC Design

By syafiq

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updated over 9 years ago by Andrew Beckett

4 replies • 14129 views
Discussion

preferred way to sweep temperature in ADEXL

Category: Custom IC Design

By danmc91

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updated over 9 years ago by Andrew Beckett

1 replies • 21620 views
Discussion

Oscillator frequency discrepancy between PSS and transient simulation

Category: Custom IC Design

By Juanelin

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updated over 9 years ago by Juanelin

2 replies • 15206 views
Discussion

need help to scale mosaic or instances

Category: Custom IC Design

By imaneet

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updated over 9 years ago by Andrew Beckett

3 replies • 14608 views
Discussion

Automate exporting ADE XL scalar outputs across History

Category: Custom IC Design

By Michele Ancis

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started over 9 years ago

0 replies • 13097 views
Discussion

Selected net in Navigator: Is it possible to change default selected net color of white?

Category: Custom IC Design

By ShawnLogan

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started over 9 years ago

0 replies • 11803 views
Discussion

Integration band for Noise type "timeaverage" Vs "jitter" method in pnoise analysis?

Category: Custom IC Design

By suresh naidu

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started over 9 years ago

0 replies • 1451 views

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