Custom IC Design

Latest Posts

Discussion

ADE windowID for a given sevSession?

Category: Custom IC Design

By yeh1

$usertype
•
updated over 9 years ago by Andrew Beckett

3 replies • 13995 views
Discussion

CDL generation with command si: how to specify a path instead of "netlist" for the resultFile ?

Category: Custom IC Design

By samung

$usertype
•
updated over 9 years ago by samung

2 replies • 4059 views
Discussion

psub and nwell via not present in 90nm layout

Category: Custom IC Design

By PS90

$usertype
•
updated over 9 years ago by ColinSutlieff

1 replies • 14205 views
Discussion

Display Issue in IC6.1.6 (64 bit) on CentOS

Category: Custom IC Design

By Raghu Rao

$usertype
•
updated over 9 years ago by Andrew Beckett

2 replies • 14229 views
Discussion

simulation a circuit with organic transistors

Category: Custom IC Design

By robert11

$usertype
•
updated over 9 years ago by ArchAngelos

4 replies • 14532 views
Discussion

AMS netlisting has failed

Category: Custom IC Design

By elfmushroom

$usertype
•
updated over 9 years ago by elfmushroom

2 replies • 17659 views
Discussion

Liberate (pass/file bisection)

Category: Custom IC Design

By kasula5

$usertype
•
started over 9 years ago

0 replies • 514 views
Discussion

Printed OFET PDK Development

Category: Custom IC Design

By ramkumarg

$usertype
•
updated over 10 years ago by robert11

2 replies • 13354 views
Discussion

Changing default settings of Virtuoso Layout XL

Category: Custom IC Design

By Clidre

$usertype
•
updated over 10 years ago by Clidre

2 replies • 18451 views
Discussion

How to fix layers after changing layer numbers in the technology file

Category: Custom IC Design

By Sheppy

$usertype
•
updated over 10 years ago by theopaone

5 replies • 18191 views
Discussion

how to attach a new device file in cadence virtuoso version 6.1.2

Category: Custom IC Design

By RAVI2100

$usertype
•
updated over 10 years ago by Quek

1 replies • 13730 views
Discussion

Making ruler value more visible

Category: Custom IC Design

By Identical

$usertype
•
updated over 10 years ago by Andrew Beckett

3 replies • 15219 views
Discussion

Parameterized Layout Design

Category: Custom IC Design

By skvishvakarma

$usertype
•
updated over 10 years ago by Sheppy

9 replies • 17239 views
Discussion

Import CDL, CDF paramter is not updated

Category: Custom IC Design

By tswong

$usertype
•
updated over 10 years ago by tswong

2 replies • 14995 views
Discussion

Virtuoso crashes when trying to instantiate a stacked VIA

Category: Custom IC Design

By Sheppy

$usertype
•
updated over 10 years ago by Sheppy

2 replies • 14026 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.