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Custom IC Design

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  • Discussion

    Monte-Carlo mean included in expressions

    Category: Custom IC Design

    By Svilen64

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    updated over 1 year ago by Andrew Beckett

    7 replies • 6493 views
  • Discussion

    Mutiport simulation using ADE-XL or ADE-L

    Category: Custom IC Design

    By Oliverz1206

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    updated over 1 year ago by Andrew Beckett

    1 replies • 5002 views
  • Discussion

    Cadence EMX: Top Shield Definition in .proc File

    Category: Custom IC Design

    By MtHopper

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    •

    started over 1 year ago

    0 replies • 5021 views
  • Discussion

    Changing Default Symbol Pin Type

    Category: Custom IC Design

    By sgcad

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    •

    updated over 1 year ago by sgcad

    6 replies • 8265 views
  • Discussion

    Interconnect the wires of particular nodes of schematic in array

    Category: Custom IC Design

    By rtyuy

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    •

    updated over 1 year ago by rtyuy

    2 replies • 5155 views
  • Discussion

    INPUT OF CADENCE SCHEMATIC FROM CODE (SUCH AS VERILOG ETC)

    Category: Custom IC Design

    By rtyuy

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    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 6415 views
  • Discussion

    Netlist without using meastro / ade

    Category: Custom IC Design

    By idann

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    •

    updated over 1 year ago by idann

    3 replies • 5486 views
  • Discussion

    PAC simulation issue, "No valid time points are specified"

    Category: Custom IC Design

    By FV031

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    updated over 1 year ago by Andrew Beckett

    3 replies • 1458 views
  • Discussion

    Simulation progress status gone in ADE Explorer (IC6.1.8-64b.500.25)

    Category: Custom IC Design

    By George Hariman

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    updated over 1 year ago by ShawnLogan

    4 replies • 6469 views
  • Discussion

    maestro results copied to another maestro results history

    Category: Custom IC Design

    By Pirate King

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    updated over 1 year ago by Andrew Beckett

    2 replies • 6045 views
  • Discussion

    device check by cellname

    Category: Custom IC Design

    By dogman4

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    •

    started over 1 year ago

    0 replies • 4599 views
  • Discussion

    Check for extraction and post layout simulation

    Category: Custom IC Design

    By Vishesh Gupta

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    •

    updated over 1 year ago by Vishesh Gupta

    5 replies • 10619 views
  • Discussion

    Maestro - saving output expressions to different folder by default

    Category: Custom IC Design

    By firebolt2

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    updated over 1 year ago by Andrew Beckett

    3 replies • 1445 views
  • Discussion

    dynamic parameter in transient sim with paramset file using design variable & arithmetic

    Category: Custom IC Design

    By vamshiky

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    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 1631 views
  • Discussion

    Techlib Warning

    Category: Custom IC Design

    By VIRAJ PANCHAL

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    •

    updated over 1 year ago by VIRAJ PANCHAL

    2 replies • 5039 views
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