Custom IC Design

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Discussion

Convert Cadence Spectre to Cadence Orcad

Category: Custom IC Design

By SC202412036016
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started 13 days ago

0 replies • 357 views
Discussion

Voltus-Fi-XL : generated path of mergedCurrents.rpt

Category: Custom IC Design

By SY202508201356
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started 13 days ago

0 replies • 364 views
Discussion

setting environment variables from schematic?

Category: Custom IC Design

By unSkilled
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started 14 days ago

0 replies • 297 views
Discussion

STB Analysis Breakpoint Selection and Nyquist Plot Support in Cadence

Category: Custom IC Design

By Eleanor Grace
•
updated 15 days ago by JankoK

3 replies • 542 views
Discussion

quantus parasitic extraction vs. SKY130 PDK

Category: Custom IC Design

By GS202507021424
•
started 22 days ago

0 replies • 397 views
Discussion

stb results different when iprobe placed at different location of the loop

Category: Custom IC Design

By a048
•
updated 22 days ago by Frank Wiedmann

3 replies • 630 views
Discussion

giolib045 "archaeology" (origin of giolib045.lib, giolib045.gds files)

Category: Custom IC Design

By GS202507021424
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started 24 days ago

0 replies • 248 views
Discussion

Schematic editor 2D array signal

Category: Custom IC Design

By kramnik
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updated 26 days ago by Andrew Beckett

1 replies • 443 views
Discussion

automate creration of calibre view from extraction for multiple extracted corners

Category: Custom IC Design

By micipici
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updated 28 days ago by Andrew Beckett

1 replies • 485 views
Discussion

Automatic routing using Cadence Virtuoso IC6.18.120

Category: Custom IC Design

By HN20250717689
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started 1 month ago

0 replies • 412 views
Discussion

How to greate guard ring for Cadence GPDK FinFet?

Category: Custom IC Design

By hesdeadJim
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updated 1 month ago by hesdeadJim

2 replies • 562 views
Discussion

ADE ViVA Plotting Template: Where is it stored and how to edit?

Category: Custom IC Design

By StephanWeber
•
updated 1 month ago by StephanWeber

2 replies • 558 views
Discussion

How to load viaGetViaOptions Function inside PCELL

Category: Custom IC Design

By Esteban Saavedra
•
updated 1 month ago by Andrew Beckett

4 replies • 593 views
Discussion

Any analogue or mixed signal Cadence FinFet layouts to share?

Category: Custom IC Design

By hesdeadJim
•
started 1 month ago

0 replies • 371 views
Discussion

verilog Syntax errors not highlighted in text editor

Category: Custom IC Design

By JavierC
•
updated 1 month ago by JavierC

6 replies • 850 views

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