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Custom IC Design

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  • Discussion

    Pin names

    Category: Custom IC Design

    By StreamCX

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    updated over 15 years ago by Andrew Beckett

    7 replies • 10395 views
  • Discussion

    LvsIgnore Properties

    Category: Custom IC Design

    By frogconsultant

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    •

    updated over 15 years ago by frogconsultant

    12 replies • 30586 views
  • Discussion

    How to implement this equation in VerilogA

    Category: Custom IC Design

    By princemahmmod

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    updated over 15 years ago by Andrew Beckett

    4 replies • 15715 views
  • Discussion

    Cadence 6 waveform error vpwl vsrc

    Category: Custom IC Design

    By StreamCX

    $usertype

    •

    updated over 15 years ago by StreamCX

    9 replies • 9074 views
  • Discussion

    Output SPEF-file from QRC contains only top level ports

    Category: Custom IC Design

    By Slawa

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    •

    updated over 15 years ago by Quek

    1 replies • 6107 views
  • Discussion

    Off-Grid pins warning in abstract generation

    Category: Custom IC Design

    By affaq

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    •

    updated over 15 years ago by Alex Soyer

    3 replies • 13868 views
  • Discussion

    subciruit initiated top-level current probe

    Category: Custom IC Design

    By Kalimero

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    •

    updated over 15 years ago by Kalimero

    5 replies • 16364 views
  • Discussion

    cadence verilog ams environment setup question

    Category: Custom IC Design

    By Wing2

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    •

    updated over 15 years ago by EricCDN

    1 replies • 18242 views
  • Discussion

    How to short small resistor for lvs purpose

    Category: Custom IC Design

    By harleyMax

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    •

    updated over 15 years ago by Andrew Beckett

    7 replies • 19258 views
  • Discussion

    Manual editing of a p2lvsfile

    Category: Custom IC Design

    By Slawa

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    •

    updated over 15 years ago by Slawa

    6 replies • 7489 views
  • Discussion

    How to change the Internal Cell names

    Category: Custom IC Design

    By sathisha

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    •

    updated over 15 years ago by Quek

    1 replies • 14530 views
  • Discussion

    ASSURA41-614: ERROR rcAddRegionTasks

    Category: Custom IC Design

    By tkhan

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    •

    updated over 15 years ago by Andrew Beckett

    3 replies • 13392 views
  • Discussion

    How to add PVS menu in virtuoso layout editor

    Category: Custom IC Design

    By shushan

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    •

    updated over 15 years ago by shushan

    2 replies • 14420 views
  • Discussion

    dose anyone know how to solve this problem???

    Category: Custom IC Design

    By Jay12

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    •

    updated over 15 years ago by Andrew Beckett

    1 replies • 12980 views
  • Discussion

    custum mdl functions in assertions

    Category: Custom IC Design

    By MarkSummers

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    •

    updated over 15 years ago by Andrew Beckett

    1 replies • 13111 views
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