Custom IC Design

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Discussion

Migration to new operating system and force compiled model recompile

Category: Custom IC Design

By JayBee
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updated 10 months ago by TomasMelander

7 replies • 4538 views
Discussion

Move Metal offgrid back on grid

Category: Custom IC Design

By TobyK
•
updated 10 months ago by RobMan

1 replies • 2416 views
Discussion

Some error while running Quantus(Assura) Parasitc extraction run form

Category: Custom IC Design

By Sameerpy
•
started 10 months ago

0 replies • 580 views
Discussion

How can I simulate based on the random mismatch generated by a previous Monte Carlo iteration?

Category: Custom IC Design

By AW202410094823
•
updated 10 months ago by AW202410094823

2 replies • 2573 views
Discussion

Quantus Coupled vs Decoupled Parasitic Extraction Results

Category: Custom IC Design

By Aida
•
updated 11 months ago by Aida

2 replies • 3272 views
Discussion

Does anyone know where I can find info on the TSMC18rf (180nm) PDK?

Category: Custom IC Design

By TheCoffeeLovingStudent
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updated 11 months ago by TheCoffeeLovingStudent

4 replies • 4385 views
Discussion

Current mirror sizing limited trans. length

Category: Custom IC Design

By JeyJey
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started 11 months ago

0 replies • 2298 views
Discussion

Saving maestro Changes After Opening in Read-Only Mode

Category: Custom IC Design

By KTBuckON
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updated 11 months ago by KTBuckON

2 replies • 2574 views
Discussion

Importing PSPICE .lib file into Virtuoso

Category: Custom IC Design

By IP202410071719
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updated 11 months ago by IP202410071719

2 replies • 3665 views
Discussion

use cadence liberate to characterize a cell that has capacitance and resistance,but failed...

Category: Custom IC Design

By TH20240830782
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updated 11 months ago by TH20240830782

2 replies • 1134 views
Discussion

regarding simulating a verilogams file in cadence for implementing mtj

Category: Custom IC Design

By JJ202409288946
•
updated 11 months ago by JJ202409288946

2 replies • 3004 views
Discussion

Virtuoso_'Analog_Design_Environment_L', 'Analog_Design_Environment_XL', and 'Analog_Design_Environment_L' License Checkout Failure IC 6.1.8

Category: Custom IC Design

By SA202410022720
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updated 11 months ago by Andrew Beckett

1 replies • 589 views
Discussion

Select Multiple Traces by Corner in ViVa

Category: Custom IC Design

By KTBuckON
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updated 11 months ago by KTBuckON

2 replies • 2838 views
Discussion

Feed results of AC analysis back to TRAN analysis (Spectre)

Category: Custom IC Design

By mikewu999
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started 11 months ago

0 replies • 2383 views
Discussion

Warning (CMI-2477) Rds is less then 0.001 gpdk90nm

Category: Custom IC Design

By AL202409293035
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updated 11 months ago by AL202409293035

2 replies • 3082 views

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