Custom IC Design

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Latency to Connect License server

Category: Custom IC Design

By Tarique mohd
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updated 1 month ago by Saloni Chhabra

3 replies • 764 views
Discussion

Parasitic Extraction Failure in Quantus - Assura

Category: Custom IC Design

By MK202507103018
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started 1 month ago

0 replies • 169 views
Discussion

Netlisting 'config' view with SPICE source file... CDF parameter m= on symbol is not printed in netlist instance call

Category: Custom IC Design

By JeffBeck
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updated 1 month ago by JeffBeck

2 replies • 495 views
Discussion

pxf or pac sampled Explanation

Category: Custom IC Design

By Patrick Chang
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started 1 month ago

0 replies • 613 views
Discussion

calcVal function works during the simulation, but fails after initiating re-evaluation

Category: Custom IC Design

By A1vis
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updated 1 month ago by A1vis

8 replies • 1687 views
Discussion

PSS/Pnoise analysis for divider circuit, input is pulse waveform from vsource with noise profile

Category: Custom IC Design

By Zaara
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started 1 month ago

0 replies • 243 views
Discussion

Tolerance relaxation when calculating DC operating point - impact on accuracy of SP analysis

Category: Custom IC Design

By Macio
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updated 1 month ago by Macio

2 replies • 460 views
Discussion

Nested ddt Operator

Category: Custom IC Design

By JF202408126026
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updated 2 months ago by JF202408126026

2 replies • 617 views
Discussion

using bus pin for inherited connection with AMS

Category: Custom IC Design

By Darrell L
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started 2 months ago

0 replies • 566 views
Discussion

Parasitic Extraction (PEX) - Tool Migration from IC6 to IC23

Category: Custom IC Design

By ranaya
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updated 2 months ago by Andrew Beckett

1 replies • 314 views
Discussion

How to apply the instance name used in the schematic to the same mosfet in layout?

Category: Custom IC Design

By MB202506119828
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updated 2 months ago by MB202506119828

10 replies • 1731 views
Discussion

IC problem in simulation

Category: Custom IC Design

By RA202502215244
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updated 2 months ago by Andrew Beckett

3 replies • 1264 views
Discussion

How can i make auto y-axis range work for each result in Corner simulation?

Category: Custom IC Design

By ichiro
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updated 2 months ago by Andrew Beckett

1 replies • 976 views
Discussion

How to exclude subckt ports in certain hierarchy branches?

Category: Custom IC Design

By John Davis
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updated 2 months ago by Andrew Beckett

1 replies • 906 views
Discussion

Veto variable permutations in Maestro

Category: Custom IC Design

By CSCNalu
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updated 2 months ago by Andrew Beckett

3 replies • 1060 views

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