Custom IC Design

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Discussion

Locating a result value from montecarlo run table in Cadence Virtuoso

Category: Custom IC Design

By Senan

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updated over 3 years ago by Senan

2 replies • 9749 views
Discussion

Dynamic paramters "temp" doesn't work? (Solver = Ultrasim, transient analysis)

Category: Custom IC Design

By SpiceMonkey

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updated over 3 years ago by Andrew Beckett

3 replies • 2364 views
Discussion

analog digital output average mean value

Category: Custom IC Design

By abdurrahman0234

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updated over 3 years ago by FormerMember

21 replies • 18585 views
Discussion

VerilogA loop generate constructs not defining multiple sub modules

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

8 replies • 13575 views
Discussion

How to measure node to node capacitance?

Category: Custom IC Design

By Holz

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updated over 3 years ago by FormerMember

3 replies • 13070 views
Discussion

variables from CDF parameters

Category: Custom IC Design

By amacSS

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updated over 3 years ago by Andrew Beckett

5 replies • 12564 views
Discussion

Set ignoredesigchangesduringrun locally / per session / per maestro cell

Category: Custom IC Design

By jehh

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updated over 3 years ago by Andrew Beckett

4 replies • 10448 views
Discussion

DRC Cadence

Category: Custom IC Design

By Zahir Kaka

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updated over 3 years ago by Andrew Beckett

1 replies • 9139 views
Discussion

ERROR (ASSEMBLER-5011) and high memory usage after some long simulations

Category: Custom IC Design

By delgsy

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updated over 3 years ago by Andrew Beckett

1 replies • 9487 views
Discussion

Coplanar wavewguide with GND plane

Category: Custom IC Design

By BoniUNIPR

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updated over 3 years ago by BoniUNIPR

2 replies • 9601 views
Discussion

verilogA

Category: Custom IC Design

By abdurrahman0234

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updated over 3 years ago by Andrew Beckett

1 replies • 9319 views
Discussion

InstallScape - failed to install component: cdsPython

Category: Custom IC Design

By bernardoleite

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updated over 3 years ago by bernardoleite

5 replies • 3405 views
Discussion

Cannot select signals to be saved in ADE Explorer/Assembler; net listing is incorrect etc.

Category: Custom IC Design

By SteveVrk

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updated over 3 years ago by FormerMember

9 replies • 5850 views
Discussion

VerilogA module instance parameter override weird behavior

Category: Custom IC Design

By AAbdelRahman

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updated over 3 years ago by AAbdelRahman

7 replies • 13343 views
Discussion

Thermal noise modeling

Category: Custom IC Design

By mahdiee86

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updated over 3 years ago by Andrew Beckett

5 replies • 12677 views

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