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Custom IC Design

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  • Discussion

    Control flow when a return from an expression is nil

    Category: Custom IC Design

    By delgsy

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    updated over 3 years ago by FormerMember

    4 replies • 11422 views
  • Discussion

    Any efficient way to do calibration using calcVal and MonteCarlo for tripple nested loop?

    Category: Custom IC Design

    By delgsy

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    updated over 3 years ago by delgsy

    2 replies • 10032 views
  • Discussion

    DC Convergence Problem When Simulating a Post-Layout r_c and r_c_cc Extraction

    Category: Custom IC Design

    By shbmsra12

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    updated over 3 years ago by Andrew Beckett

    5 replies • 12067 views
  • Discussion

    xi0.m1: Effective length is less than or equal to zero?? newbie in cadence!

    Category: Custom IC Design

    By archive

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    updated over 3 years ago by Andrew Beckett

    4 replies • 16761 views
  • Discussion

    leaf cell issue with using diffstbprobe

    Category: Custom IC Design

    By kenc184

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    updated over 3 years ago by kenc184

    2 replies • 10777 views
  • Discussion

    Saving the image of many output signals in Cadence Virtuoso

    Category: Custom IC Design

    By Senan

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    updated over 3 years ago by Senan

    2 replies • 10285 views
  • Discussion

    Is it normal for DeCap to get 0 value leakage power when running liberate?

    Category: Custom IC Design

    By sherryshe

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    updated over 3 years ago by Guangjun Cao

    1 replies • 9643 views
  • Discussion

    How to backannotate Monte-Carlo DCOP simulation results to schematic

    Category: Custom IC Design

    By delgsy

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    updated over 3 years ago by delgsy

    2 replies • 9884 views
  • Discussion

    Statistical file for Monte Carlo analysis

    Category: Custom IC Design

    By Hemaresearch

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    updated over 3 years ago by Andrew Beckett

    3 replies • 11480 views
  • Discussion

    Spectre 16775 Warning

    Category: Custom IC Design

    By DeepaMohan

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    updated over 3 years ago by DeepaMohan

    4 replies • 10131 views
  • Discussion

    Is it possible to do this in VerilogA?

    Category: Custom IC Design

    By Svilen64

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    updated over 3 years ago by Svilen64

    11 replies • 13205 views
  • Discussion

    Issue in accessing PSF directory with ocean script.

    Category: Custom IC Design

    By dskang

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    updated over 3 years ago by FormerMember

    2 replies • 10501 views
  • Discussion

    Violations display in ADE L

    Category: Custom IC Design

    By FabioDiFazio

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    updated over 3 years ago by FabioDiFazio

    2 replies • 10559 views
  • Discussion

    bandwidth function in Virtuoso calculator

    Category: Custom IC Design

    By sidm

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    updated over 3 years ago by sidm

    2 replies • 16960 views
  • Discussion

    Using existing maestro view

    Category: Custom IC Design

    By sidm

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    updated over 3 years ago by sidm

    4 replies • 12067 views
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