Custom IC Design

Latest Posts

Discussion

Using FinFETs in OrCAD Capture

Category: Custom IC Design

By Sati

$usertype
•
updated over 4 years ago by Sati

2 replies • 11128 views
Discussion

Question on PSS+PNoise simulation for a Track and Hold circuit

Category: Custom IC Design

By YutaoLiu

$usertype
•
updated over 4 years ago by Andrew Beckett

11 replies • 14126 views
Discussion

Post Layout simulation for multi-finger transistors

Category: Custom IC Design

By Senan

$usertype
•
updated over 4 years ago by FormerMember

11 replies • 15162 views
Discussion

noise sim always report 0% of Total

Category: Custom IC Design

By monglebest

$usertype
•
updated over 4 years ago by Andrew Beckett

8 replies • 13481 views
Discussion

Working model for MDL language - A query

Category: Custom IC Design

By MicheleAncis

$usertype
•
updated over 4 years ago by FormerMember

2 replies • 1766 views
Discussion

Adding wreal input and output bus in verilog-AMS

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 4 years ago by RFStuff

5 replies • 15341 views
Discussion

HISIM-HV models

Category: Custom IC Design

By pejmank

$usertype
•
updated over 4 years ago by Andrew Beckett

2 replies • 11456 views
Discussion

Verilog-A white_noise function returns 0 in transient noise simulation

Category: Custom IC Design

By threepwood06

$usertype
•
updated over 4 years ago by threepwood06

4 replies • 12123 views
Discussion

Canceling out the parasitic diode in Layout

Category: Custom IC Design

By Hossein Eslahi

$usertype
•
started over 4 years ago

0 replies • 11074 views
Discussion

Current density check for layout design

Category: Custom IC Design

By Senan

$usertype
•
updated over 4 years ago by Senan

4 replies • 13540 views
Discussion

"ERROR: attempt to access a quantity that depends on the time derivative" in Verilog-A

Category: Custom IC Design

By rhanna

$usertype
•
updated over 4 years ago by Andrew Beckett

13 replies • 5511 views
Discussion

Bindkeys in ADE Explorer/Assembler

Category: Custom IC Design

By crossi

$usertype
•
updated over 4 years ago by crossi

5 replies • 2608 views
Discussion

illegal connection CAD warning message

Category: Custom IC Design

By Senan

$usertype
•
started over 4 years ago

0 replies • 10935 views
Discussion

"ncelab: *E,CUVPOM " Errors... is invalid or has multiple connections

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 4 years ago by Andrew Beckett

1 replies • 8765 views
Discussion

Issues in using a Verilog-A output as input to a Verilog-AMS block

Category: Custom IC Design

By RFStuff

$usertype
•
updated over 4 years ago by Andrew Beckett

2 replies • 12988 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.