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Custom IC Design

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  • Discussion

    RelXpert Error with intermediate file input.p1

    Category: Custom IC Design

    By PatriciaG

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    updated over 8 years ago by Andrew Beckett

    1 replies • 13499 views
  • Discussion

    PSS and number of harmonics in crystal oscillators

    Category: Custom IC Design

    By PeppeW90

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    updated over 8 years ago by Andrew Beckett

    1 replies • 14220 views
  • Discussion

    layout-xl schematic numbering update

    Category: Custom IC Design

    By NoelCFC

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    updated over 8 years ago by NoelCFC

    2 replies • 13470 views
  • Discussion

    DRC License Error

    Category: Custom IC Design

    By legolas

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    updated over 8 years ago by Andrew Beckett

    3 replies • 15465 views
  • Discussion

    Transient simulation of a crystal oscillator

    Category: Custom IC Design

    By PeppeW90

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    •

    updated over 8 years ago by Tawna

    1 replies • 17291 views
  • Discussion

    SRAM Design

    Category: Custom IC Design

    By Naina123

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    started over 8 years ago

    0 replies • 14528 views
  • Discussion

    Standard Cell Libraries (Basic)

    Category: Custom IC Design

    By AndreyVolk

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    •

    updated over 8 years ago by AndreyVolk

    2 replies • 6407 views
  • Discussion

    Phase Margin Calculation

    Category: Custom IC Design

    By netbug

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 16592 views
  • Discussion

    Error running DRC on Assura - "The Assura DRC Run Failed"

    Category: Custom IC Design

    By fanelli

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    updated over 8 years ago by fanelli

    2 replies • 2632 views
  • Discussion

    creating custom cell

    Category: Custom IC Design

    By asetji

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    •

    started over 8 years ago

    0 replies • 13672 views
  • Discussion

    problem simulating a sub-circuit (spectre model) with ade

    Category: Custom IC Design

    By asetji

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    •

    updated over 8 years ago by asetji

    3 replies • 15680 views
  • Discussion

    VerilogA vs. built-in device models

    Category: Custom IC Design

    By samer1

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    updated over 8 years ago by samer1

    2 replies • 13838 views
  • Discussion

    How to avoid compiling Verilog/sytemVerilog views every time you netlist (AMS)?

    Category: Custom IC Design

    By iguerra

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    updated over 8 years ago by Andrew Beckett

    3 replies • 3495 views
  • Discussion

    cds_get_analog_value or cgav is not correct

    Category: Custom IC Design

    By nthoangga

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 14147 views
  • Discussion

    MDL: create a new waveform and save it into a wavefile

    Category: Custom IC Design

    By PatrikOsgnach

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    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 14180 views
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