Custom IC Design

Latest Posts

Discussion

how to set up IPVS to use multiple threads

Category: Custom IC Design

By Gaussian

$usertype
•
updated over 10 years ago by Quek

1 replies • 13120 views
Discussion

Has anyone ever ran into a QRC extraction "RC-coupled" with empty .SUBCKT for macro cell

Category: Custom IC Design

By ttran0671

$usertype
•
updated over 10 years ago by Quek

1 replies • 848 views
Discussion

QRC Extraction - Assura

Category: Custom IC Design

By Paolo Minotti

$usertype
•
updated over 10 years ago by Quek

1 replies • 1994 views
Discussion

Simulation of extraced view fails, due to missing supply nets in netlist

Category: Custom IC Design

By marten

$usertype
•
updated over 10 years ago by Quek

1 replies • 13188 views
Discussion

[Solved] MIM capacitor is not being recognized during LVS

Category: Custom IC Design

By Subrata

$usertype
•
updated over 10 years ago by Quek

3 replies • 17029 views
Discussion

Is it possible to run Assura LVS under Ubuntu 14.04?

Category: Custom IC Design

By R Wodnicki

$usertype
•
updated over 10 years ago by Quek

1 replies • 13542 views
Discussion

How do I get Assura to save DRC markers to the layout database like DIVA?

Category: Custom IC Design

By Michael L

$usertype
•
updated over 10 years ago by Quek

1 replies • 13747 views
Discussion

Assura RC deck working in PVS

Category: Custom IC Design

By nads

$usertype
•
updated over 10 years ago by Quek

1 replies • 13906 views
Discussion

Avoid unnecessary large file size in Cadence Transient Simulation

Category: Custom IC Design

By MenghanSun

$usertype
•
updated over 10 years ago by Subrata

1 replies • 14609 views
Discussion

ADEXL: detecting process corners

Category: Custom IC Design

By kawan

$usertype
•
updated over 10 years ago by kawan

6 replies • 16842 views
Discussion

vsource voltage level always 1V, val0 & val1 missing in netlist

Category: Custom IC Design

By marten

$usertype
•
updated over 10 years ago by marten

4 replies • 1858 views
Discussion

ADEXL: Preloading Multiple Runs

Category: Custom IC Design

By kawan

$usertype
•
updated over 10 years ago by kawan

6 replies • 14540 views
Discussion

Problem with QRC execution

Category: Custom IC Design

By w888ku

$usertype
•
updated over 10 years ago by w888ku

2 replies • 13955 views
Discussion

Ultrasim Error for Stitching

Category: Custom IC Design

By Cuong Truong

$usertype
•
updated over 10 years ago by Cuong Truong

2 replies • 13162 views
Discussion

[SOLVED] Verilog-AMS code doesn't compile with genvar

Category: Custom IC Design

By msharma

$usertype
•
updated over 10 years ago by Andrew Beckett

1 replies • 2728 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.