Custom IC Design

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Importing verilog to Cadence schematic

Category: Custom IC Design

By Wonyoung

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updated over 13 years ago by weebey

10 replies • 21552 views
Discussion

IC5141_USR6 in RHEL5

Category: Custom IC Design

By Satya

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updated over 13 years ago by DanL

8 replies • 14563 views
Discussion

Is it possible to convert layout.oa/sch.oa database format to text

Category: Custom IC Design

By ramiabr

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updated over 13 years ago by Quek

1 replies • 2023 views
Discussion

spectre

Category: Custom IC Design

By arundevnkumar

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updated over 13 years ago by Quek

1 replies • 12888 views
Discussion

setting snapMode to anyAngle in Virtuoso 6.1.5 using env var (SOLVED)

Category: Custom IC Design

By MOSFET

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updated over 13 years ago by Andrew Beckett

2 replies • 14487 views
Discussion

Defining length in an expression to be evaluated

Category: Custom IC Design

By canbaltaci

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updated over 13 years ago by Andrew Beckett

3 replies • 13811 views
Discussion

How to compile verilog file to valid IC6.x cellview from command prompt

Category: Custom IC Design

By aleksand1975

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updated over 13 years ago by aleksand1975

2 replies • 13716 views
Discussion

Simulating basic circuits using spice models

Category: Custom IC Design

By tc2566

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started over 13 years ago

0 replies • 13239 views
Discussion

monte carlo trimmed simulation in adexl (cadence 6)

Category: Custom IC Design

By Trevor1981

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updated over 13 years ago by Trevor1981

2 replies • 16076 views
Discussion

Question on Cadence Capacitor Output Templates

Category: Custom IC Design

By heartsoar

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updated over 13 years ago by Andrew Beckett

6 replies • 16153 views
Discussion

how to vary frequency in virtuoso

Category: Custom IC Design

By PSASWALE

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updated over 13 years ago by PSASWALE

2 replies • 14324 views
Discussion

Temperature coefficient of capacitance by metal to substrate in QRC extraction

Category: Custom IC Design

By bjbit

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updated over 13 years ago by Quek

1 replies • 13868 views
Discussion

Power calculation

Category: Custom IC Design

By RAJ JOHRI

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updated over 13 years ago by Quek

1 replies • 13741 views
Discussion

cap ground signal 'gndRefNode' cannot be found while running Assura QRC

Category: Custom IC Design

By shushan

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updated over 13 years ago by tingsu

6 replies • 9337 views
Discussion

No width segment in QuickView layout window

Category: Custom IC Design

By Teru

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updated over 13 years ago by Andrew Beckett

3 replies • 13449 views

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